Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 56)

Chapter 5: 1G/10GbE MAC Design Example 5–11
1G/10GbE Testbench
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
3. Launch the Quartus II software and open the altera_eth_10g_mac_base_kr_top.v
file from the project directory.
4. Open the Quartus II Tcl Console window by pointing to Utility Windows on the
View menu and then selecting Tcl Console. In the Quartus II Tcl Console window,
type the following command to set up the project environment:
source setup_proj.tcl
r
5. Launch Qsys from the Tools menu and open altera_eth_10g_mac_base_kr.qsys in
the File menu.
6. On the Generation tab, select Verilog simulation model.
By default, the system will be running in 1G/10Gb Ethernet mode. To run in
backplane-KR mode, edit the following Backplane Ethernet 10GBASE-KR PHY
instances of channels 1 and 0:
■ IP variant = Backplane-KR
■ Turn on Enable Automatic Speed Detection.
■ Turn on Enable Auto-negotiation.
7. Click Generate to generate the system.
8. Launch the ModelSim simulator software.
9. Change the working directory to <project directory>/<design example
directory>/testbench in the File menu.
10. Run the following command to set up the required libraries, compile the
generated IP Functional simulation model, and exercise the simulation model with
the provided testbench:
do tb_run.tcl
r
By default the system will be running in 1G/10Gb Ethernet mode. To run in
backplane-KR mode, open the tb.sv file and change the MODE_1G10G_KR_BAR
parameter to 0, then run the command.
11. The ModelSim transcript pane in Main window displays messages from the
testbench reflecting the current task being performed.
Upon a successful simulation, the simulator displays the following RX Statistics
and TX Statistics:
# framesOK = 8
# framesErr = 0
# framesCRCErr = 0
# octetsOK = 5142
# pauseMACCtrlFrames = 0
# ifErrors = 0
# unicastFramesOK = 6
# unicastFramesErr = 0
# multicastFramesOK = 1
# multicastFramesErr = 0
# broadcastFramesOK = 1