Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 160)

B–4 Appendix B: Time-of-Day (ToD) Clock
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
B.6. ToD Clock Configuration Register Space
Table B–6 describes the ToD clock register space.
period_clk Input 1
Clock for the ToD clock. The clock must be in the
same clock domain as tx_time_of_day and
rx_time_of_day
in the MAC function. The
expected frequency for the 10GbE MAC is
156.25 MHz.
period_rst_n Input 1
Assert this signal to reset period_clk to the
same clock domain as tx_time_of_day and
rx_time_of_day
in the MAC function.
Table B–5. Avalon-ST Transmit Interface Signals for ToD Clock (Part 2 of 2)
Signal Direction Width Description
Table B–6. ToD Clock Registers (Part 1 of 2)
Byte
Offset
Name R/W Description
HW
Reset
0x00 SecondsH RW
■ Bits 0 to 15: High-order 16-bit second field.
■ Bits 16 to 31: Not used.
0x0
0x04 SecondsL RW Bits 0 to 32: Low-order 32-bit second field. 0x0
0x08 NanoSec RW Bits 0 to 32: 32-bit nanosecond field. 0x0
0x0C Reserved — Reserved for future use —
0x10 Period RW
The period for the frequency adjustment.
■ Bits 0 to 15: Period in fractional nanosecond
(PERIOD_FNS).
■ Bits 16 to 19: Period in nanosecond (PERIOD_NS).
■ Bits 20 to 31: Not used.
The default value for the period depends on the f
MAX
of
the MAC function. For example, if f
MAX
= 125-MHz, the
period is 8-ns (PERIOD_NS = 0x0008 and PERIOD_FNS
= 0x0000).
n
0x14 AdjustPeriod RW
The period for the offset adjustment.
■ Bits 0 to 15: Period in fractional nanosecond
(ADJPERIOD_FNS).
■ Bits 16 to 19: Period in nanosecond
(ADJPERIOD_NS).
■ Bits 20 to 31: Not used.
0x0
0x18 AdjustCount RW
■ Bits 0 to 19: The number of AdjustPeriod clock
cycles used during offset adjustment.
■ Bits 20 to 31: Not used.
0x0