Altera 10-Gbps Ethernet MAC MegaCore Function User Manual

Page 106

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8–12

Chapter 8: Registers

MAC Registers

10-Gbps Ethernet MAC MegaCore Function User Guide

February 2014

Altera Corporation

0x0C10

rx_stats_unicast FramesErr

(2)

RO

0x0

Bit 0—The number of errored unicast
frames received or transmitted, excluding
control frames.

36-bit width register:

0x0C10 and 0x0C11 = bits [31:0]

0x1C10 and 0x1C11 = bits [35:32]

0x0C11

0x1C10

tx_stats_unicast FramesErr

(2)

0x1C11

0x0C12

rx_stats_multicast FramesOK

RO

0x0

Bit 0—The number of good multicast
frames that are successfully received or
transmitted, excluding control frames.

36-bit width register:

0x0C12 and 0x0C13 = bits [31:0]

0x1C12 and 0x1C13 = bits [35:32]

0x0C13

0x1C12

tx_stats_multicast FramesOK

0x1C13

0x0C14

rx_stats_multicast FramesErr

(2)

RO

0x0

Bit 0—The number of errored multicast
frames received or transmitted, excluding
control frames.

36-bit width register:

0x0C14 and 0x0C15 = bits [31:0]

0x1C14 and 0x1C15 = bits [35:32]

0x0C15

0x1C14

tx_stats_multicast FramesErr

(2)

0x1C15

0x0C16

rx_stats_broadcast FramesOK

RO

0x0

Bit 0—The number of good broadcast
frames received or transmitted, excluding
control frames.

36-bit width register:

0x0C16 and 0x0C17 = bits [31:0]

0x1C16 and 0x1C17 = bits [35:32]

0x0C17

0x1C16

tx_stats_broadcast FramesOK

0x1C17

0x0C18

rx_stats_broadcast FramesErr

(2)

RO

0x0

Bit 0—The number of errored broadcast
frames received or transmitted, excluding
control frames.

36-bit width register:

0x0C18 and 0x0C19 = bits [31:0]

0x1C18 and 0x1C19 = bits [35:32]

0x0C19

0x1C18

tx_stats_broadcast FramesErr

(2)

0x1C19

0x0C1A

rx_stats_etherStats Octets

RO

0x0

Bit 0—The total number of octets received
or transmitted. This count includes good,
errored, and invalid frames.

0x0C1B

0x1C1A

tx_stats_etherStats Octets

0x1C1B

0x0C1C

rx_stats_etherStatsPkts

RO

0x0

Bit 0—The total number of good, errored,
and invalid frames received or transmitted.

36-bit width register:

0x0C1C and 0x0C1D = bits [31:0]

0x1C1C and 0x1C1D = bits [35:32]

0x0C1D

0x1C1C

tx_stats_etherStatsPkts

0x1C1D

Table 8–2. MAC Registers (Part 11 of 15)

Word

Offset

Register Name

Access

Reset
Value

Description

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