Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 50)

Chapter 5: 1G/10GbE MAC Design Example 5–5
1G/10GbE Design Example Files
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
1 This design example uses a 19-bit width address bus to access the base address of
components other than the MAC.
f For more information about the 10GBASE-KR, refer to the 10GBASE-KR PHY IP Core
chapter in the Altera Transceiver PHY IP Core User Guide.
5.3. 1G/10GbE Design Example Files
Figure 5–3 shows the directory structure for the 1G/10GbE design examples and
testbenches.
Table 5–3 lists the files in the ..\altera_eth_10g_mac_base_kr directory.
10GBASE-KR Channel 0 0x80000
10GBASE-KR Channel 1 0x80800
Configure Reconfiguration Channel 0 0x80400
Configure Reconfiguration Channel 1 0x80500
RX FIFO (Avalon-ST Single-Clock FIFO) Channel 0 0x10400
TX FIFO (Avalon-ST Single-Clock FIFO) Channel 0 0x10600
RX FIFO (Avalon-ST Single-Clock FIFO) Channel 1 0x30400
TX FIFO (Avalon-ST Single-Clock FIFO) Channel 1 0x30600
Table 5–2. Base Addresses of 1G/10GbE Design Example Components
Component Base Address
Figure 5–3. 1G/10GbE Design Example Folders
Table 5–3. 1G/10GbE Design Example Files
File Name Description
altera_eth_10g_mac_base_kr_top.v
The top-level entity file of the design example for
verification in hardware.
altera_eth_10g_mac_base_kr_top.sdc
The Quartus II SDC constraint file for use with
the TimeQuest timing analyzer.
setup_proj.tcl
A Tcl script that creates a new Quartus II project
and sets up the project environment for your
design example.
altera_eth_10g_mac_base_kr.qsys
A Qsys file for the 1G/10GbE MAC and 10G
BASE-KR PHY design example with the
Quartus II software targeting the Stratix V device.
reconfig.v
A top-level entity file for the transceiver
reconfiguration controller IP.
<ip_lib>/ethernet/altera_eth_10g_design_example
altera_eth_10g_mac_base_kr
testbench
reconfig