Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 45)

Chapter 4: 10GbE MAC with IEEE1588v2 Design Example 4–7
10GbE with IEEE 1588v2 Testbench
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
4.5.4. 10GbE with IEEE 1588v2 Testbench Simulation Flow
Upon a simulated power-on reset, each testbench performs the following operations:
1. Initializes the DUT by configuring the following options through the Avalon-MM
interface:
■ Configures the MAC. In the MAC, enables address insertion on the transmit
path and sets the transmit and receive primary MAC address to EE-CC-88-CC-
AA-EE. Also enables CRC insertion on transmit path.
■ Configures Timestamp Unit in the MAC, by setting periods and path delay
adjustments of the clocks.
■ Configures ToD clock by loading a predefined time value.
■ Configures clock mode of Packet Classifier to Ordinary Clock mode.
2. Starts packet transmission with different clock mode. The testbench sends a total
of four packets:
■ 64-byte basic Ethernet frames
■ 1-step PTP Sync message over Ethernet
■ 1-step PTP Sync message over UDP/IPv4 with VLAN tag
■ 2-step PTP Sync message over UDP/IPv6 with stacked VLAN tag
3. Configures clock mode of Packet Classifier to End-to-end Transparent Clock
mode.
4. Starts packet transmission. The testbench sends a total of three packets:
■ 1-step PTP Sync message over Ethernet
■ 2-step PTP Sync message over UDP/IPv4 with VLAN tag
■ 1-step PTP Sync message over UDP/IPv6 with stacked VLAN tag
5. Ends the transmission.
4.5.5. Simulating 10GbE with IEEE 1588v2 Testbench with ModelSim
Simulator
To use the ModelSim simulator to simulate the testbench design, follow these steps:
1. Copy the respective design example directory to your preferred project directory:
altera_eth_10g_mac_base_r_1588 from
<ip library>/ethernet/altera_eth_10g_design_example.
2. Launch Qsys from the Tools menu and open the
altera_eth_10g_mac_base_r_1588.qsys file.
3. On the Generation tab, select either a Verilog HDL or VHDL simulation model.
4. Click Generate to generate the simulation and synthesis files.
5. Run the following command to set up the required libraries, to compile the
generated IP Functional simulation model, and to exercise the simulation model
with the provided testbench:
do tb_run_simulation.tcl
r