Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 112)

8–18 Chapter 8: Registers
MAC Registers for IEEE 1588v2 Feature
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
8.2. MAC Registers for IEEE 1588v2 Feature
Table 8–5 describes the MAC register space for the 10GbE MAC with IEEE 1588v2
feature.
Table 8–5. MAC Registers for 1GbE MAC with IEEE 1588v2 Feature (Part 1 of 2)
Word Offset Name R/W Description
HW
Reset
0x0110
(10 Gbps mode)/
0x0118
(1 Gbps, 10 Mbps,
and 100 Mbps
mode)
rx_period RW
Clock period for timestamp adjustment on the receive
datapath. The period register is multiplied by the
number of stages separating actual timestamp and
the GMII bus.
■ Bits 0 to 15: Period in fractional nanoseconds
(RX_PERIOD_FNS).
■ Bits 16 to 19: Period in nanoseconds
(RX_PERIOD_NS).
■ Bits 20 to 31: Not used.
The default value for the period is 6.4. For
156.25-MHz clock, set this register to 6.4 ns.
0x66666
0x1110
(10 Gbps mode)/
0x1118
(1 Gbps, 10 Mbps,
and 100M bps
mode))
tx_period RW
Clock period for timestamp adjustment on the
transmit datapath. The period register is multiplied by
the number of stages separating actual timestamp
and the GMII bus.
■ Bits 0 to 15: Period in fractional nanoseconds
(TX_PERIOD_FNS).
■ Bits 16 to 19: Period in nanoseconds
(TX_PERIOD_NS).
■ Bits 20 to 31: Not used.
The default value for the period is 6.4. For
156.25-MHz clock, set this register to 6.4 ns.
0x66666
0x0112
(10 Gbps mode)/
0x011A
(1 Gbps, 10 Mbps,
and 100 Mbps
mode)
rx_adjust_fns RW
Static timing adjustment in fractional nanoseconds
for outbound timestamps on the receive datapath.
■ Bits 0 to 15: Timing adjustment in fractional
nanoseconds.
■ Bits 16 to 31: Not used.
0x0
0x1112
(10 Gbps mode)/
0x111A
(1 Gbps, 10 Mbps,
and 100 Mbps
mode)
tx_adjust_fns RW
Static timing adjustment in fractional nanoseconds
for outbound timestamps on the transmit datapath.
■ Bits 0 to 15: Timing adjustment in fractional
nanoseconds.
■ Bits 16 to 31: Not used.
0x0