Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 21)

Chapter 3: 10GbE MAC Design Examples 3–3
10GbE Design Example Components
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
The design example comprises the following components:
■ 10GbE Ethernet MAC—the MAC IP core with default settings. This IP core
includes memory-based statistics counters.
■ XAUI PHY or 10GBASE-R PHY—the PHY IP core with default settings. The XAUI
PHY is set to Hard XAUI by default.
■ Ethernet Loopback— the loopback module provides a mechanism for you to
verify the functionality of the MAC and PHY. Refer to
Section 3.2.0.1, Ethernet
Loopback Module for more information about this module.
■ RX and TX FIFO buffers—Avalon-ST Single-Clock or Dual-Clock FIFO cores that
buffer receive and transmit data between the MAC and client. These FIFO buffers
are 64 bits wide and 512 bits deep. The default configuration is Avalon-ST
Single-Clock FIFO, which operates in store and forward mode and you can
configure it to provide packet-based flushing when an error occurs.
1 To enable the Avalon-ST Single-Clock FIFO to operate in cut through mode,
turn off the Use store and forward parameter in the Avalon-ST Single
Clock FIFO
parameter editor.
■ Configuration and debugging tools—provides access to the registers of the
following components via the Avalon Memory-Mapped (Avalon-MM) interface:
MAC, MDIO, Ethernet loopback, PHY, and FIFO buffers. The provided testbench
includes an Avalon driver which uses the pipeline bridge to access the registers.
You can use the system console to access the registers via the JTAG to Avalon
Master Bridge core when verifying the design in the hardware.
f To learn more about the components, refer to the respective documents:
■ XAUI PHY and 10GBASE-R PHY, refer to Altera Transceiver PHY IP Core User
Guide .
■ Avalon-ST Single-Clock or Dual-Clock FIFO, JTAG to Avalon Master Bridge, and
MDIO cores, refer to
Embedded Peripherals IP User Guide .
■ Pipeline bridge, refer to Avalon Memory-Mapped Bridges in volume 4 of the Quartus
II Handbook.
■ System Console, refer to Analyzing and Debugging Designs with the System Console in
volume 3 of the Quartus II Handbook.
3.2.0.1. Ethernet Loopback Module
You can enable one of the following loopback types:
■ Local loopback—turn on this loopback to verify the functionality of the MAC
during simulation. When you enable the local loopback, the Ethernet loopback
module takes the transmit frame from the MAC XGMII TX and loops it back to the
MAC XGMII RX datapath. During this cycle, the loopback module also forwards
the TX frame to the PHY. While the local loopback is turned on, the loopback
module ignores any frame it receives from the PHY.