Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 97)

Chapter 8: Registers 8–3
MAC Registers
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
0x002 –
0x03F
Reserved — — Reserved for future use.
RX Pad/CRC Remover (0x040:0x07F)
0x040 rx_padcrc_control RW 0x1
Padding and CRC removal (through the
avalon_st_rx_data
signal).
■ Bit 0 configures CRC removal.
0—Retains the CRC field in receive packets.
1—Removes the CRC field from receive
packets.
■ Bit 1 configures padding and CRC removal.
0—Retains the padding bytes and CRC
field.
1—Removes the padding bytes and CRC
field from receive packets. The setting of
this bit takes precedence over bit 0.
■ Bits 2 to 31 are reserved.
0x041 –
0x07F
Reserved — — Reserved for future use.
RX CRC Checker (0x080:0x0BF)
0x080 rx_crccheck_control RW 0x2
CRC checking:
■ Bit 0—Always set this bit to 0.
■ Bit 1 configures CRC checking.
0—Ignores the CRC field.
1—Checks the CRC field.
■ Bits 2 to 31 are reserved.
0x081 –
0x0BF
Reserved — — Reserved for future use.
RX Packet Overflow (0x0C0:0x0FF)
Table 8–2. MAC Registers (Part 2 of 15)
Word
Offset
Register Name Access
Reset
Value
Description