Document Outline

• 100G Interlaken MegaCore Function User Guide
• Contents
• 1. About This MegaCore Function
  • Features
    • IP Core Supported Combinations of Number of Lanes and Data Rate
    • IP Core Theoretical Raw Aggregate Bandwidth
  • Device Family Support
  • IP Core Verification
  • Performance and Resource Utilization
  • Device Speed Grade Support
  • Release Information
• 2. Getting Started With the 100G Interlaken IP Core
  • Installing and Licensing IP Cores
    • OpenCore Plus IP Evaluation
  • Specifying the 100G Interlaken IP Core Parameters and Options
  • Files Generated for Arria V GZ and Stratix V Variations
  • Files Generated for Arria 10 Variations
  • Simulating the100G Interlaken IP Core
  • Integrating Your IP Core in Your Design
    • Pin Assignments
    • Transceiver Logical Channel Numbering
    • Adding the Reconfiguration Controller
      • Generating the Reconfiguration Controller
      • Connecting the Reconfiguration Controller to the IP Core
    • Adding the External PLL
  • Compiling the Full Design and Programming the FPGA
• 3. 100G Interlaken IP Core Parameter Settings
  • Number of Lanes
  • Meta Frame Length in Words
  • Data Rate
  • Transceiver Reference Clock Frequency
  • Include Advanced Error Reporting and Handling
  • Enable M20K ECC Support
  • Include Diagnostic Features
  • Include In-Band Flow Control Block
  • Number of Calendar Pages
  • TX Scrambler Seed
  • Transfer Mode Selection
  • Data Format
• 4. Functional Description
  • Interfaces Overview
    • Application Interface
    • Interlaken Interface
    • Out‑of‑Band Flow Control Interface
    • Management Interface
    • Transceiver Control Interfaces
      • Transceiver Reconfiguration Controller Interface
      • Arria 10 External PLL Interface
      • Arria 10 Transceiver Reconfiguration Interface
  • High Level Block Diagram
  • Clocking and Reset Structure for IP Core
    • 100G Interlaken IP Core Clock Signals
    • IP Core Reset
    • IP Core Reset Sequence with the Reconfiguration Controller
  • Interleaved and Packet Modes
  • Dual Segment Mode
  • M20K ECC Support
  • 100G Interlaken IP Core Transmit Path
    • 100G Interlaken IP Core Transmit User Data Interface Examples
      • 100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example
      • 100G Interlaken IP Core Packet Mode Operation Example
      • 100G Interlaken IP Core Back-Pressured Packet Transfer Example
      • 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit Example
    • 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side
    • 100G Interlaken IP Core Transmit Path Blocks
      • 100G Interlaken IP Core TX Transmit Buffer
      • 100G Interlaken IP Core TX MAC
      • 100G Interlaken IP Core TX PCS
      • 100G Interlaken IP Core TX PMA
  • 100G Interlaken IP Core Receive Path
    • 100G Interlaken IP Core Receive User Data Interface Examples
      • 100G Interlaken IP Core Receiver Side Example
      • 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive Example
    • 100G Interlaken IP Core RX Errored Packet Handling
      • 100G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
    • In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface
    • 100G Interlaken IP Core Receive Path Blocks
      • 100G Interlaken IP Core RX PMA
      • 100G Interlaken IP Core RX PCS
      • 100G Interlaken IP Core RX MAC
      • 100G Interlaken IP Core RX Regroup Block
• 5. 100G Interlaken MegaCore Function Signals
  • 100G Interlaken IP Core Clock Interface Signals
  • 100G Interlaken IP Core Reset Interface Signals
  • 100G Interlaken IP Core User Data Transfer Interface Signals
  • 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
  • 100G Interlaken IP Core Management Interface
  • Device Dependent Signals
    • Transceiver Reconfiguration Controller Interface Signals
    • Arria 10 External PLL Interface Signals
    • Arria 10 Transceiver Reconfiguration Interface Signals
• 6. 100G Interlaken IP Core Register Map
• 7. 100G Interlaken IP Core Testbench
  • 100G Interlaken IP Core Testbench Interface Signals
  • Testbench Simulation Behavior
  • Running the Testbench With the Example Design
    • Setting Up the Testbench Example
    • Simulating the Example Design
• 8. 100G Interlaken IP Core Test Features
  • Internal Serial Loopback Mode
  • External Loopback Mode
  • PRBS Generation and Validation
    • Setting up PRBS Mode in Arria V and Stratix V Devices
    • Setting up PRBS Mode in Arria 10 Devices
  • CRC32 Error Injection
  • CRC24 Error Injection
• 9. Advanced Parameter Settings
  • Hidden Parameters
    • Include Temp Sense
    • RXFIFO Address Width
    • SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)
  • Modifying Hidden Parameter Values
• 10. Out-of-Band Flow Control in the 100G Interlaken MegaCore Function
  • Out-of-Band Flow Control Block Clocks
  • TX Out‑of‑Band Flow Control Signals
  • RX Out-of-Band Flow Control Signals
• A. Performance and Fmax Requirements for 100G Ethernet Traffic
• B. Additional Information
  • Document Revision History
  • How to Contact Altera
  • Typographic Conventions