Altera 100G Interlaken MegaCore Function User Manual
100g interlaken megacore function user guide
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Table of contents
Document Outline
- 100G Interlaken MegaCore Function User Guide
- Contents
- 1. About This MegaCore Function
- 2. Getting Started With the 100G Interlaken IP Core
- Installing and Licensing IP Cores
- Specifying the 100G Interlaken IP Core Parameters and Options
- Files Generated for Arria V GZ and Stratix V Variations
- Files Generated for Arria 10 Variations
- Simulating the100G Interlaken IP Core
- Integrating Your IP Core in Your Design
- Compiling the Full Design and Programming the FPGA
- 3. 100G Interlaken IP Core Parameter Settings
- Number of Lanes
- Meta Frame Length in Words
- Data Rate
- Transceiver Reference Clock Frequency
- Include Advanced Error Reporting and Handling
- Enable M20K ECC Support
- Include Diagnostic Features
- Include In-Band Flow Control Block
- Number of Calendar Pages
- TX Scrambler Seed
- Transfer Mode Selection
- Data Format
- 4. Functional Description
- Interfaces Overview
- High Level Block Diagram
- Clocking and Reset Structure for IP Core
- Interleaved and Packet Modes
- Dual Segment Mode
- M20K ECC Support
- 100G Interlaken IP Core Transmit Path
- 100G Interlaken IP Core Receive Path
- 5. 100G Interlaken MegaCore Function Signals
- 100G Interlaken IP Core Clock Interface Signals
- 100G Interlaken IP Core Reset Interface Signals
- 100G Interlaken IP Core User Data Transfer Interface Signals
- 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
- 100G Interlaken IP Core Management Interface
- Device Dependent Signals
- 6. 100G Interlaken IP Core Register Map
- 7. 100G Interlaken IP Core Testbench
- 8. 100G Interlaken IP Core Test Features
- 9. Advanced Parameter Settings
- 10. Out-of-Band Flow Control in the 100G Interlaken MegaCore Function
- A. Performance and Fmax Requirements for 100G Ethernet Traffic
- B. Additional Information