Altera 100G Interlaken MegaCore Function - Manual (Page 2)

Contents
About This MegaCore Function......................................................................... 1-1
Features......................................................................................................................................................... 1-1
IP Core Supported Combinations of Number of Lanes and Data Rate................................... 1-2
IP Core Theoretical Raw Aggregate Bandwidth..........................................................................1-2
Device Family Support................................................................................................................................1-2
IP Core Verification.....................................................................................................................................1-3
Performance and Resource Utilization.....................................................................................................1-3
Device Speed Grade Support......................................................................................................................1-5
Release Information.....................................................................................................................................1-5
Getting Started With the 100G Interlaken IP Core............................................2-1
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
Specifying the 100G Interlaken IP Core Parameters and Options .......................................................2-2
Files Generated for Arria V GZ and Stratix V Variations......................................................................2-3
Files Generated for Arria 10 Variations....................................................................................................2-4
Simulating the100G Interlaken IP Core................................................................................................... 2-6
Integrating Your IP Core in Your Design................................................................................................ 2-6
Pin Assignments...............................................................................................................................2-6
Transceiver Logical Channel Numbering.....................................................................................2-7
Adding the Reconfiguration Controller..................................................................................... 2-10
Adding the External PLL.............................................................................................................. 2-12
Compiling the Full Design and Programming the FPGA....................................................................2-14
100G Interlaken IP Core Parameter Settings..................................................... 3-1
Number of Lanes..........................................................................................................................................3-1
Meta Frame Length in Words....................................................................................................................3-2
Data Rate....................................................................................................................................................... 3-2
Transceiver Reference Clock Frequency...................................................................................................3-2
Include Advanced Error Reporting and Handling..................................................................................3-3
Enable M20K ECC Support........................................................................................................................3-4
Include Diagnostic Features....................................................................................................................... 3-4
Include In-Band Flow Control Block........................................................................................................3-5
Number of Calendar Pages.........................................................................................................................3-5
TX Scrambler Seed.......................................................................................................................................3-5
Transfer Mode Selection.............................................................................................................................3-6
Data Format..................................................................................................................................................3-6
Functional Description....................................................................................... 4-1
Interfaces Overview..................................................................................................................................... 4-1
TOC-2 About This MegaCore Function
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