Altera 100G Interlaken MegaCore Function - Manual (Page 7)

FPGA Device Families
Final support — The IP core is verified with final timing models for this device family. The IP core meets all
functional and timing requirements for the device family and can be used in production designs.
The following table shows the level of support offered by the 100G Interlaken MegaCore function for each
Altera device family.
Table 1-4: Device Family Support
Device Family Support
Stratix V (GS, GT, and GX) Final
Arria V (GZ) Final
Arria 10 Preliminary
Other device families No support
IP Core Verification
Before releasing a version of the 100G Interlaken IP core, Altera runs comprehensive regression tests in
the current version of the Quartus ® II software. These tests use standalone methods. These files are tested
in simulation and hardware to confirm functionality. Altera tests and verifies the 100G Interlaken IP core
in hardware for different platforms and environments.
Constrained random techniques generate appropriate stimulus for the functional verification of the IP
core. Functional coverage metrics measure the quality of the random stimulus, and ensure that all
important features are verified.
Performance and Resource Utilization
UG-01128
2015.05.04
IP Core Verification 1-3
About This MegaCore Function Altera Corporation
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