Altera 100G Interlaken MegaCore Function - Manual (Page 40)

M20K ECC Support
If you turn on Enable M20K ECC support in your Stratix V or Arria 10 100G Interlaken IP core
variation, the IP core takes advantage of the built-in device support for ECC checking in all M20K blocks
configured in the IP core on the device. The feature performs single-error correct, double-adjacent-error
correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in
your IP core. The IP core reports ECC error statistics in the registers
CNT_ERR_TX
,
CNT_UNCOR_TX
,
CNT_ERR_RX
, and
CNT_UNCOR_RX
at offsets 0x122 through 0x125.
This feature enhances data reliability but increases latency and resource utilization. Without the ECC
feature, a single M20K memory block can support a data path width of 40 bits. With the ECC feature,
eight of those bits are dedicated to the ECC, and an M20K memory block can support a maximum data
path width of 32 bits. Therefore, when M20K ECCsupport is turned on the IP core configures additional
M20K memory blocks. The ECC check adds latency to the path through the memory block, and increases
the amount of device memory used by your IP core.
Related Information
• Enable M20K ECC Support on page 3-4
• 100G Interlaken IP Core Register Map on page 6-1
Describes the
CNT_ERR_TX
,
CNT_UNCOR_TX
,
CNT_ERR_RX
, and
CNT_UNCOR_RX
100G Interlaken IP core
M20K ECC status registers.
• Embedded Memory Blocks in Stratix V Devices
Information about the built-in ECC feature in Stratix V devices.
• Embedded Memory Blocks in Arria 10 Devices
Information about the built-in ECC feature in Arria 10 devices.
100G Interlaken IP Core Transmit Path
The 100G Interlaken MegaCore function accepts application data from up to 256 channels and combines
it into a single data stream in which data is labeled with its source channel. The 100G Interlaken TX MAC
and PCS blocks format the data into protocol-compliant bursts and insert Idle words where required.
100G Interlaken IP Core Transmit User Data Interface Examples
The following examples illustrate how to use the Altera 100G Interlaken IP core TX user data interface:
100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example on page 4-10
100G Interlaken IP Core Packet Mode Operation Example on page 4-12
100G Interlaken IP Core Back-Pressured Packet Transfer Example on page 4-13
100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit Example on page 4-15
100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example
In Interleaved Mode, you are responsible for scheduling the burst. You need to drive an extra pair of
signals, Start of Burst (SOB) and End of Burst (EOB), to indicate the burst boundary. You can send the
traffic in packet order or interleaved order, as long as you set the SOB and EOB flags correctly to establish
the data boundaries.
4-10 M20K ECC Support
UG-01128
2015.05.04
Altera Corporation Functional Description
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