Altera 100G Interlaken MegaCore Function - Manual (Page 57)

100G Interlaken IP Core Receive Path Blocks
Figure 4-13: 100G Interlaken IP Core Receive Path
irx_chan[7:0]
irx_num_valid[7:0]
irx_sob[1:0]
irx_eob
irx_sop[1:0]
irx_eopbits[3:0]
irx_dout_words[511:0]
irx_calendar[16 x n - 1:0]
irx_err
Transceiver Blocks
clk_rx_common rx_mac_clk rx_usr_clk
RX
PCS
RX
PMA
RX
MAC
RX
Regroup
rx_pin[m - 1:0]
The 100G Interlaken IP core receive data path has the following four main functional blocks:
100G Interlaken IP Core RX PMA on page 4-27
100G Interlaken IP Core RX PCS on page 4-27
100G Interlaken IP Core RX MAC on page 4-27
100G Interlaken IP Core RX Regroup Block on page 4-28
100G Interlaken IP Core RX PMA
The 100G Interlaken MegaCore function RX PMA deserializes data that the IP core receives on the serial
lines of the Interlaken link.
100G Interlaken IP Core RX PCS
RX PCS logic is an embedded hard macro and does not consume FPGA soft logic elements.
The 100G Interlaken MegaCore function RX PCS block performs the following functions to retrieve the
data:
• Detects word lock and word synchronization.
• Checks running disparity.
• Reverses gearboxing and 64/67B encoding.
• Descrambles the data.
• Delineates meta frame boundaries.
• Performs CRC32 checking.
• Sends lane status information to the calendar and status blocks, if Include in-band flow control
functionality is turned on.
100G Interlaken IP Core RX MAC
To recover a packet or burst, the RX MAC takes data from each of the PCS lanes and reassembles the
packet or burst.
UG-01128
2015.05.04
100G Interlaken IP Core Receive Path Blocks 4-27
Functional Description Altera Corporation
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