Altera 100G Interlaken MegaCore Function - Manual (Page 51)

4'b1011 on
irx_eopbits
to indicate that the data the IP core transfers to the application in this cycle are
the final words of the packet, and that in the final word of the packet, only three bytes are valid data. The
value the IP core drives on
irx_chan
indicates this burst targets channel 4.
In cycle 4, the
irx_num_valid[7:4]
signal has the value of zero, which means this cycle is an idle cycle.
In cycle 5, the IP core sends another single-cycle data burst to channel 2, by asserting
irx_sob[1]
and
irx_eob
to indicate this data is both the start and end of the burst. The IP core does not assert
irx_sop[1]
, because this burst is not start of packet data.
irx_eopbits
has the value of 4'b0000,
indicating this burst is also not end of packet data. This data follows the data burst transfered in cycles 1
and 2, within the same packet the IP core is sending to channel 2.
In cycle 6, the IP core sends a start of packet, single-cycle data burst to channel 3.
In cycles 7 and 8, the IP core sends a two-cycle data packet in one two-cycle burst. In cycle 8, the second
data cycle, the IP core drives the value of two on
irx_num_valid[7:4]
and the value of 4'b1011 on
irx_eopbits
, to tell the application that in this clock cycle, the two most significant words of the data
symbol contain valid data and the remaining words do not contain valid data, and that in the second of
these two words, only the three most significant bytes contain valid data.
UG-01128
2015.05.04
100G Interlaken IP Core Receiver Side Example 4-21
Functional Description Altera Corporation
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