Altera 100G Interlaken MegaCore Function - Manual (Page 89)

RX Register Offset Bits Meaning Action
3 0x164 [10] Enable RX PRBS clock Set this bit to the value of 1 to enable the
RX PRBS clock.
After you activate an IP core that targets an Arria V or Stratix V device to generate PRBS output, it
immediately begins transmitting PRBS output on the Interlaken link. After you enable the IP core to
receive PRBS input, you can check the receive PRBS status in the 100G Interlaken IP core PRBS status
registers (
RX_PRBS_DONE, RX_PRBS_ERR,
and
RX_PRBS_COUNT
).
After your testing is complete, you must reset these register bits to their default values to enable normal
operation.
Related Information
• 100G Interlaken IP Core Register Map on page 6-1
Describes the PRBS status registers.
• PRBS Generation and Validation on page 8-2
Lists the supported PRBS polynomials.
• Altera Transceiver PHY IP Core User Guide
Setting up PRBS Mode in Arria 10 Devices
To enable the IP core to generate PRBS output, for each Interlaken lane, you must program the relevant
hard PCS registers to enable the PRBS generator clock, to set the test_enable bit, and to select the PRBS
polynomial. To enable the IP core to receive PRBS input, for each Interlaken lane, you must program the
relevant hard PCS registers to enable the PRBS receiver clock and to select the expected PRBS polynomial,
in addition to some bookkeeping tasks. If you perform your PRBS testing in loopback mode, you must
enable the IP core to both generate and receive PRBS sequences. After you set the hard PCS registers for
PRBS mode, you must perform a soft reset of the transceiver.
The PRBS feature is available only if you turn on Include diagnostic features in the 100G Interlaken
parameter editor.
This section describes the register values you must program. For instructions to program the registers that
activate the PRBS test feature in your Arria 10 100G Interlaken IP core, refer to the hard PCS register
information in the Arria 10 Transceiver PHY User Guide. You program the hard PCS registers using the
100G Interlaken IP core Arria 10 transceiver reconfiguration interface.
8-4 Setting up PRBS Mode in Arria 10 Devices
UG-01128
2015.05.04
Altera Corporation 100G Interlaken IP Core Test Features
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