Altera 100G Interlaken MegaCore Function - Manual (Page 16)

Simulating the100G Interlaken IP Core
You can simulate your 100G Interlaken MegaCore function variation using any of the vendor-specific
IEEE encrypted functional simulation models which are generated in the new <instance name>_sim
subdirectory of your project directory.
The 100G Interlaken MegaCore function supports the Synopsys VCS, Cadence NC Sim, and Mentor
Graphics Modelsim-SE simulators.
The 100G Interlaken IP core generates only a Verilog HDL simulation model and testbench. The IP core
parameter editor appears to offer you the option of generating a VHDL simulation model, but this IP core
does not support a VHDL simulation model or testbench.
For more information about functional simulation models for Altera IP cores, refer to the Simulating
Altera Designs chapter in volume 3 of the Quartus II Handbook.
If you specify the models are in Verilog HDL when you parameterize your IP core variation, the Quartus
II software generates a testbench which demonstrates the resetting, clocking, and toggling of the
100G Interlaken IP core user interfaces.
Related Information
• 100G Interlaken IP Core Testbench on page 7-1
When you generate the IP core, the Quartus II software generates a testbench.
• Simulating Altera Designs
Integrating Your IP Core in Your Design
After you generate your 100G Interlaken IP core variation, you can instantiate it in the RTL for your
design. When you integrate your IP core instance in your design, you must pay attention to the following
items.
Pin Assignments
When you integrate your 100G Interlaken MegaCore function instance in your design, you must make
appropriate pin assignments. You do not need to specify pin assignments for simulation. However, you
should make the pin assignments before you compile, to provide direction to the Quartus II Fitter and to
specify the signals that should be assigned to device pins.
You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are
simulating and not ready to map the design to hardware. Do not create virtual pins for clock or Interlaken
link data signals.
For the Arria 10 device family, you must configure a PLL external to the 100G Interlaken IP core. The
required number of PLLs depends on the distribution of your Interlaken lane data pins in the different
A10 transceiver blocks.
Related Information
Quartus II Help
For information about the Quartus II software, including virtual pins.
2-6 Simulating the100G Interlaken IP Core
UG-01128
2015.05.04
Altera Corporation Getting Started With the 100G Interlaken IP Core
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