Altera 100G Interlaken MegaCore Function - Manual (Page 84)

Note: If the IP core is in dual segment mode, the testbench sends 65-byte bursts on the TX user data
transfer interface. If the IP core is in single segment, Interleaved mode, the testbench sends 128-
byte bursts.
3. Performs a sequence of register read and write operations to demonstrate register access.
4. Resets the 100G Interlaken IP core again.
5. After the reset sequence completes, sends an additional sequence of Interlaken packets of the same
type as in Step 2.
6. Completes the sequence of packets and reports success or failure.
The testbench is not parameterizable — you cannot modify the packet sequence that the testbench
generates for a specific DUT. However, Altera provides the testbench files in cleartext format, and you can
modify the testbench for your own testing purposes. The packet generator included in the testbench can
be used to generate pseudo-random or specific sizes packets.
The packet checker included in the testbench provides the following basic packet checking capabilities:
• Checks that the transmitted packet sequence is not violated
• Checks that the received data matches expected values
Running the Testbench With the Example Design
Perform the following steps to simulate the testbench example:
1.
Setting Up the Testbench Example on page 7-3
2. Simulating the Example Design on page 7-3
Setting Up the Testbench Example
When you generate your 100G Interlaken IP core, if you specify Verilog HDL IP core models, the
resulting file structure includes the example design and the testbench.
Related Information
Specifying the 100G Interlaken IP Core Parameters and Options on page 2-2
Provides instructions to generate the DUT.
Simulating the Example Design
Altera provides simulation scripts for simulating the testbench in the Mentor Graphics Modelsim SE
simulator. However, you can write your own scripts to simulate the testbench in other Altera-supported
simulators. Your script should check that the SOP and EOP counts match after simulation is complete.
To simulate the example design using the Altera-provided scripts, perform the following steps:
1. Ensure IP core generation is complete.
2. Start the Mentor Graphics ModelSim-SE simulation tool.
3. Change directory to the following folder, which contains the generated testbench:
a. <variation>
_sim/ilk_core/testbench for Arria V GZ and Stratix V IP core variations.
b. <variation>
/ilk_core_ <version> /sim/testbench for Arria 10 IP core variations.
4. Type the following command:
do vlog.do
The testbench generates a series of packets on the IP core TX user data transfer interface, loops the
resulting Interlaken data transmissions back to the IP core on the Interlaken link, and checks the
UG-01128
2015.05.04
Running the Testbench With the Example Design 7-3
100G Interlaken IP Core Testbench Altera Corporation
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