Altera 100G Interlaken MegaCore Function User Manual
Page 69
Signal Name
Direction
Width (Bits)
Description
tx_lanes_
aligned
Output
1
All of the transmitter lanes are aligned and are
ready to send traffic.
itx_hungry
Output
1
A dynamic status flag indicating that a
downstream buffer which supplies data to the
PCS is running empty. The IP core handles this
situation by inserting IDLE symbols (IDLE
control words) in the packet stream. Therefore,
this signal does not indicate an error.
This signal is asserted for the duration of the
condition it indicates.
The PCS runs continuously with the provided
data or inserted IDLE symbols. This signal is
usually asserted immediately after the IP core
comes out of reset. However, the signal can also
be asserted during normal operation, and is not
a cause for concern.
itx_overflow
Output
1
An error flag indicating that the PCS buffer is
currently overflowing. This signal is asserted for
the duration of the overflow condition: it is
asserted in the first clock cycle in which the
overflow occurs, and remains asserted until the
PCS buffer pointers indicate that no overflow
condition exists.
itx_underflow
Output
1
An error flag indicating that the PCS buffer is
currently underflowed. In normal operation,
this signal may be asserted temporarily
immediately after the 100G Interlaken IP core
comes out of reset. It is asserted as a single cycle
wide pulse.
Real-Time Receiver Status Signals (Synchronous with rx_usr_clk )
sync_locked
Output
Number of lanes
Receive lane has locked on the remote
transmitter Meta Frame. These signals are level
signals: all bits are expected to stay high unless a
problem occurs on the serial line.
word_locked
Output
Number of lanes
Receive lane has identified the 67-bit word
boundaries in the serial stream. These signals
are level signals: all bits are expected to stay high
unless a problem occurs on the serial line.
rx_lanes_
aligned
Output
1
All of the receiver lanes are aligned and are
ready to receive traffic. This signal is a level
signal.
UG-01128
2015.05.04
100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5-11
100G Interlaken MegaCore Function Signals
Altera Corporation