100g interlaken ip core test features, Internal serial loopback mode, 100g interlaken ip core test features -1 – Altera 100G Interlaken MegaCore Function User Manual
Page 86: Internal serial loopback mode -1
100G Interlaken IP Core Test Features
8
2015.05.04
UG-01128
Depending on the features you turn on in the 100G Interlaken parameter editor, your 100G Interlaken IP
core supports the following test features:
on page 8-1
The 100G Interlaken IP core supports an internal TX to RX serial loopback mode.
The 100G Interlaken IP core operates correctly in an external loopback configuration.
PRBS Generation and Validation
on page 8-2
Internal Serial Loopback Mode
The 100G Interlaken IP core supports an internal TX to RX serial loopback mode.
To turn on internal serial loopback:
• Reset the IP core by asserting the active low
reset_n
signal.
• After reset completes, set the value of bits [NUM_LANES-1:0] of the
LOOPBACK
register at offset 0x12
to all ones.
Note: Refer to "IP Core Reset" for information about the required wait period for register access.
• Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the
rx_lanes_aligned
output signal. After the RX lanes are aligned, the IP core is in internal serial loopback mode.
Resetting the IP core turns off internal serial loopback. To turn off internal serial loopback:
• Reset the IP core by asserting the active low
reset_n
signal. Resetting the IP core sets the value of bits
[NUM_LANES-1:0] of the
LOOPBACK
register at offset 0x12 to all zeroes.
• Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the
rx_lanes_aligned
output signal. After the RX lanes are aligned, the IP core is in normal operational mode.
Related Information
on page 4-5
Describes the required delay from reset to successful register access attempts.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html
. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134