Altera 100G Interlaken MegaCore Function - Manual (Page 3)

Application Interface.......................................................................................................................4-1
Interlaken Interface..........................................................................................................................4-1
Out-of-Band Flow Control Interface.............................................................................................4-2
Management Interface.................................................................................................................... 4-2
Transceiver Control Interfaces.......................................................................................................4-2
High Level Block Diagram..........................................................................................................................4-4
Clocking and Reset Structure for IP Core................................................................................................ 4-4
100G Interlaken IP Core Clock Signals.........................................................................................4-5
IP Core Reset.................................................................................................................................... 4-5
IP Core Reset Sequence with the Reconfiguration Controller.................................................. 4-7
Interleaved and Packet Modes................................................................................................................... 4-7
Dual Segment Mode.................................................................................................................................... 4-8
M20K ECC Support...................................................................................................................................4-10
100G Interlaken IP Core Transmit Path.................................................................................................4-10
100G Interlaken IP Core Transmit User Data Interface Examples........................................ 4-10
100G Interlaken IP Core In-Band Calendar Bits on Transmit Side....................................... 4-17
100G Interlaken IP Core Transmit Path Blocks........................................................................4-18
100G Interlaken IP Core Receive Path....................................................................................................4-19
100G Interlaken IP Core Receive User Data Interface Examples........................................... 4-20
100G Interlaken IP Core RX Errored Packet Handling........................................................... 4-24
In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface.......4-26
100G Interlaken IP Core Receive Path Blocks...........................................................................4-27
100G Interlaken MegaCore Function Signals.....................................................5-1
100G Interlaken IP Core Clock Interface Signals....................................................................................5-1
100G Interlaken IP Core Reset Interface Signals.....................................................................................5-3
100G Interlaken IP Core User Data Transfer Interface Signals............................................................ 5-4
100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals................................. 5-9
100G Interlaken IP Core Management Interface.................................................................................. 5-13
Device Dependent Signals........................................................................................................................ 5-14
Transceiver Reconfiguration Controller Interface Signals.......................................................5-15
Arria 10 External PLL Interface Signals......................................................................................5-15
Arria 10 Transceiver Reconfiguration Interface Signals.......................................................... 5-16
100G Interlaken IP Core Register Map...............................................................6-1
100G Interlaken IP Core Testbench....................................................................7-1
100G Interlaken IP Core Testbench Interface Signals............................................................................7-2
Testbench Simulation Behavior.................................................................................................................7-2
Running the Testbench With the Example Design.................................................................................7-3
Setting Up the Testbench Example................................................................................................7-3
Simulating the Example Design.....................................................................................................7-3
100G Interlaken IP Core Test Features.............................................................. 8-1
Internal Serial Loopback Mode..................................................................................................................8-1
About This MegaCore Function TOC-3
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