Document Outline

• Embedded Peripheral IP User Guide
• Contents
• Introduction
  • Tool Support
  • Obsolescence
  • Device Support
  • Document Revision History
• SDRAM Controller Core
  • Core Overview
  • Functional Description
    • Avalon-MM Interface
    • Off-Chip SDRAM Interface
      • Signal Timing and Electrical Characteristics
      • Synchronizing Clock and Data Signals
      • Clock Enable (CKE) not Supported
      • Sharing Pins with other Avalon-MM Tri-State Devices
    • Board Layout and Pinout Considerations
    • Performance Considerations
      • Open Row Management
      • Sharing Data and Address Pins
      • Hardware Design and Target Device
  • Configuration
    • Memory Profile Page
    • Timing Page
  • Hardware Simulation Considerations
    • SDRAM Controller Simulation Model
    • SDRAM Memory Model
      • Using the Generic Memory Model
      • Using the SDRAM Manufacturer's Memory Model
  • Example Configurations
  • Software Programming Model
  • Clock, PLL and Timing Considerations
    • Factors Affecting SDRAM Timing
    • Symptoms of an Untuned PLL
    • Estimating the Valid Signal Window
    • Example Calculation
  • Document Revision History
• Tri-State SDRAM
  • Feature Description
    • Block Diagram
  • Configuration Parameter
    • Memory Profile Page
    • Timing Page
  • Interface
  • Reset and Clock Requirements
  • Architecture
    • Avalon-MM Slave Interface and CSR
    • Block Level Usage Model
  • Document Revision History
• Compact Flash Core
  • Core Overview
  • Functional Description
  • Required Connections
  • Software Programming Model
    • HAL System Library Support
    • Software Files
    • Register Maps
      • Ide Registers
      • Ctl Registers
      • Cfctl Register
      • idectl Register
  • Document Revision History
• Common Flash Interface Controller Core
  • Core Overview
  • Functional Description
  • Configuration
    • Attributes Page
      • Preset Settings
      • Setting Size
    • Timing page
  • Software Programming Model
    • HAL System Library Support
      • Limitations
    • Software Files
  • Document Revision History
• EPCS Serial Flash Controller Core
  • Core Overview
  • Functional Description
    • Avalon-MM Slave Interface and Registers
  • Configuration
  • Software Programming Model
    • HAL System Library Support
    • Software Files
  • Document Revision History
• JTAG UART Core
  • Core Overview
  • Functional Description
    • Avalon Slave Interface and Registers
    • Read and Write FIFOs
    • JTAG Interface
    • Host-Target Connection
  • Configuration
    • Configuration Page
      • Write FIFO Settings
      • Read FIFO Settings
    • Simulation Settings
      • Simulated Input Character Stream
      • Prepare Interactive Windows
  • Hardware Simulation Considerations
  • Software Programming Model
    • HAL System Library Support
      • Driver Options: Fast vs. Small Implementations
      • ioctl() Operations
    • Software Files
    • Accessing the JTAG UART Core via a Host PC
    • Register Map
      • Data Register
      • Control Register
    • Interrupt Behavior
  • Document Revision History
• UART Core
  • Core Overview
  • Functional Description
    • Avalon-MM Slave Interface and Registers
    • RS-232 Interface
    • Transmitter Logic
    • Receiver Logic
    • Baud Rate Generation
  • Instantiating the Core
    • Configuration Settings
      • Baud Rate Options
      • Baud Rate (bps) Setting
      • Baud Rate Can Be Changed By Software Setting
      • Data Bits, Stop Bits, Parity
      • Synchronizer Stages
      • Flow Control
      • Streaming Data (DMA) Control
    • Simulation Settings
      • Simulated RXD-Input Character Stream
      • Prepare Interactive Windows
      • Simulated Transmitter Baud Rate
  • Simulation Considerations
  • Software Programming Model
    • HAL System Library Support
      • Driver Options: Fast vs Small Implementations
      • ioct() Operations
      • Limitations
    • Software Files
    • Register Map
      • rxdata Register
      • txdata Register
      • status Register
      • control Register
      • divisor Register (Optional)
      • endofpacket Register (Optional)
    • Interrupt Behavior
  • Document Revision History
• 16550 UART
  • Core Overview
  • Feature Description
    • Unsupported Features
    • Interface
    • General Architecture
    • Configuration Parameters
    • DMA Support
    • FPGA Resource Usage
    • Timing and Fmax
    • Avalon-MM Slave
      • Read behavior
      • Write behavior
    • Overrun/Underrun Conditions
      • Overrun
      • Receive Overrun Behavior
      • Transmit Overrun Behavior
      • Underrun
    • Hardware Auto Flow-Control
    • Clock and Baud Rate Selection
  • Software Programming Model
    • Overview
    • Supported Features
    • Unsupported Features
    • Configuration
    • 16550 UART API
      • Public APIs
      • Private APIs
      • UART Device Structure
    • Driver Examples
  • Document Revision History
• SPI Core
  • Core Overview
  • Functional Description
    • Example Configurations
    • Transmitter Logic
    • Receiver Logic
    • Master and Slave Modes
      • Master and Slave Modes
      • Slave Mode Operation
      • Multi-Slave Environments
    • Avalon-MM Interface
  • Configuration
    • Master/Slave Settings
      • Number of Select (SS_n) Signals
      • SPI Clock (sclk) Rate
      • Specify Delay
    • Data Register Settings
    • Timing Settings
  • Software Programming Model
    • Hardware Access Routines
      • alt_avalon_spi_command()
    • Software Files
    • Register Map
      • rxdata Register
      • txdata Register
      • status Register
      • control Register
      • slaveselect Register
  • Document Revision History
• Optrex 16207 LCD Controller Core
  • Core Overview
  • Functional Description
  • Software Programming Model
    • HAL System Library Support
    • Displaying Characters on the LCD
    • Software Files
    • Register Map
    • Interrupt Behavior
  • Document Revision History
• PIO Core
  • Core Overview
  • Functional Description
    • Data Input and Output
    • Edge Capture
    • IRQ Generation
  • Example Configurations
    • Avalon-MM Interface
  • Configuration
    • Basic Settings
      • Width
      • Direction
      • Output Port Reset Value
      • Output Register
    • Input Options
      • Edge Capture Register
      • Interrupt
    • Simulation
  • Software Programming Model
    • Software Files
    • Register Map
      • data Register
      • direction Register
      • interruptmask Register
      • edgecapture Register
      • outset and outclear Register
    • Interrupt Behavior
    • Software Files
  • Document Revision History
• Avalon-ST Serial Peripheral Interface Core
  • Core Overview
  • Functional Description
    • Interfaces
    • Operation
    • Timing
    • Limitations
  • Configuration
  • Document Revision History
• PCI Lite Core
  • Core Overview
  • Performance and Resource Utilization
  • Functional Description
    • PCI-Avalon Bridge Blocks
    • Avalon-MM Ports
    • Prefetchable Avalon-MM Master
    • Non-Prefectchable Avalon-MM Master
    • I/O Avalon-MM Master
    • PCI Bus Access Slave
    • Control Register Access (CRA) Avalon-MM Slave
    • Master and Target Performance
      • Master Performance
      • Target Performance
    • PCI-to-Avalon Address Translation
    • Avalon-to-PCI Address Translation
    • Avalon-To-PCI Read and Write Operation
      • Avalon-to-PCI Write Request
      • Avalon-to-PCI Read Request
    • Ordering of Requests
    • PCI Interrupt
  • Configuration
    • PCI Timing Constraint Files
  • Simulation Considerations
    • Master Transactor (mstr_tranx)
    • Simulation Flow
  • Document Revision History
• MDIO Core
  • Functional Description
    • MDIO Frame Format (Clause 45)
    • MDIO Clock Generation
    • Interfaces
    • Operation
      • Write Operation
      • Read Operation
  • Parameter
  • Configuration Registers
  • Document Revision History
• On-Chip FIFO Memory Core
  • Core Overview
  • Functional Description
    • Avalon-MM Write Slave to Avalon-MM Read Slave
    • Avalon-ST Sink to Avalon-ST Source
    • Avalon-MM Write Slave to Avalon-ST Source
    • Avalon-ST Sink to Avalon-MM Read Slave
    • Status Interface
    • Clocking Modes
  • Configuration
    • FIFO Settings
    • Interface Parameters
  • Software Programming Model
    • HAL System Library Support
    • Software Files
  • Programming with the On-Chip FIFO Memory
    • Software Control
    • Software Example
  • On-Chip FIFO Memory API
    • altera_avalon_fifo_init()
    • altera_avalon_fifo_read_status()
    • altera_avalon_fifo_read_ienable()
    • altera_avalon_fifo_read_almostfull()
    • altera_avalon_fifo_read_almostempty()
    • altera_avalon_fifo_read_event()
    • altera_avalon_fifo_read_level()
    • altera_avalon_fifo_clear_event()
    • altera_avalon_fifo_write_ienable()
    • altera_avalon_fifo_write_almostfull()
    • altera_avalon_fifo_write_almostempty()
    • altera_avalon_write_fifo()
    • altera_avalon_write_other_info()
    • altera_avalon_fifo_read_fifo()
  • Document Revision History
• Avalon-ST Multi-Channel Shared Memory FIFO Core
  • Core Overview
  • Performance and Resource Utilization
  • Functional Description
    • Interfaces
    • Operation
  • Parameters
  • Software Programming Model
    • HAL System Library Support
    • Register Map
  • Document Revision History
• SPI Slave/JTAG to Avalon Master Bridge Cores
  • Core Overview
  • Functional Description
  • Parameters
  • Document Revision History
• Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores
  • Functional Description
    • Interfaces
    • Operation—Avalon-ST Bytes to Packets Converter Core
    • Operation—Avalon-ST Packets to Bytes Converter Core
  • Document Revision History
• Avalon Packets to Transactions Converter Core
  • Core Overview
  • Functional Description
    • Interfaces
    • Operation
  • Document Revision History
• Scatter-Gather DMA Controller Core
  • Core Overview
    • Example Systems
    • Comparison of SG-DMA Controller Core and DMA Controller Core
  • Resource Usage and Performance
  • Functional Description
    • Functional Blocks and Configurations
    • DMA Descriptors
    • Error Conditions
  • Parameters
  • Simulation Considerations
  • Software Programming Model
    • HAL System Library Support
    • Software Files
    • Register Maps
    • DMA Descriptors
    • Timeouts
  • Programming with SG-DMA Controller
    • Data Structure
    • SG-DMA API
    • alt_avalon_sgdma_do_async_transfer()
    • alt_avalon_sgdma_do_sync_transfer()
    • alt_avalon_sgdma_construct_mem_to_mem_desc()
    • alt_avalon_sgdma_construct_stream_to_mem_desc()
    • alt_avalon_sgdma_construct_mem_to_stream_desc()
    • alt_avalon_sgdma_check_descriptor_status()
    • alt_avalon_sgdma_register_callback()
    • alt_avalon_sgdma_start()
    • alt_avalon_sgdma_stop()
    • alt_avalon_sgdma_open()
  • Document Revision History
• Altera Modular Scatter-Gather DMA
  • Overview
  • Feature Description
    • mSGDMA Interfaces and Parameters
      • Component Interface
        • Descriptor Slave Port
        • CSR Slave Port
        • Response Port
        • Component Parameters
      • Component GUI
    • mSGDMA Descriptors
      • Read and Write Address Fields
      • Length Field
      • Sequence Number Field
      • Read and Write Burst Count Fields
      • Read and Write Stride Fields
      • Control Field
    • Register Map of mSGDMA
      • Status Register
      • Control Register
    • Unsupported Feature
    • Document Revision History
• DMA Controller Core
  • Core Overview
  • Functional Description
    • Setting Up DMA Transactions
    • The Master Read and Write Ports
    • Addressing and Address Incrementing
  • Parameters
    • DMA Parameters (Basic)
    • Advanced Options
  • Software Programming Model
    • HAL System Library Support
    • Software Files
    • Register Map
    • Interrupt Behavior
  • Document Revision History
• Video Sync Generator and Pixel Converter Cores
  • Core Overview
  • Video Sync Generator
    • Functional Description
    • Parameters
    • Signals
    • Timing Diagrams
  • Pixel Converter
    • Functional Description
    • Parameters
    • Signals
  • Hardware Simulation Considerations
  • Document Revision History
• Interval Timer Core
  • Core Overview
  • Functional Description
    • Avalon-MM Slave Interface
  • Configuration
    • Timeout Period
    • Counter Size
    • Hardware Options
    • Configuring the Timer as a Watchdog Timer
  • Software Programming Model
    • HAL System Library Support
    • Software Files
    • Register Map
    • Interrupt Behavior
  • Document Revision History
• Mutex Core
  • Core Overview
  • Functional Description
  • Configuration
  • Software Programming Model
    • Software Files
    • Hardware Access Routines
  • Mutex API
    • altera_avalon_mutex_is_mine()
    • altera_avalon_mutex_first_lock()
    • altera_avalon_mutex_lock()
    • altera_avalon_mutex_open()
    • altera_avalon_mutex_trylock()
    • altera_avalon_mutex_unlock()
  • Document Revision History
• Mailbox Core
  • Core Overview
  • Functional Description
  • Configuration
  • Software Programming Model
    • Software Files
    • Programming with the Mailbox Core
  • Mailbox API
    • altera_avalon_mailbox_close()
    • altera_avalon_mailbox_get()
    • altera_avalon_mailbox_open()
    • altera_avalon_mailbox_pend()
    • altera_avalon_mailbox_post()
  • Document Revision History
• Vectored Interrupt Controller Core
  • Core Overview
  • Functional Description
    • External Interfaces
    • Functional Blocks
  • Register Maps
  • Parameters
  • Altera HAL Software Programming Model
    • Software Files
    • Macros
    • Data Structure
    • VIC API
      • alt_vic_sw_interrupt_set()
      • alt_vic_sw_interrupt_clear()
      • alt_vic_sw_interrupt_status()
      • alt_vic_irq_set_level()
    • Run-time Initialization
    • Board Support Package
      • altera_vic_driver.enable_preemption
      • altera_vic_driver.enable_preemption_into_new_register_set
      • altera_vic_driver.enable_preemption_rs_<n>
      • altera_vic_driver.linker_section
      • altera_vic_driver.<name>.vec_size
      • altera_vic_driver.<name>.irq<n>_rrs
      • altera_vic_driver.<name>.irq<n>_ril
      • altera_vic_driver.<name>.irq<n>_rnmi
      • Default Settings for RRS and RIL
      • VIC BSP Design Rules for Altera Hal Implementation
      • RTOS Considerations
  • Document Revision History
• Avalon-ST JTAG Interface Core
  • Functional Description
    • Interfaces
    • Core Behavior
      • Bytestream Operation
      • JTAG Debug Operation
    • Parameters
  • Document Revision History
• System ID Core
  • Core Overview
  • Functional Description
  • Configuration
  • Software Programming Model
    • alt_avalon_sysid_test()
  • Document Revision History
• Performance Counter Core
  • Core Overview
  • Functional Description
    • Section Counters
    • Global Counter
    • Register Map
    • System Reset
  • Configuration
    • Define Counters
    • Multiple Clock Domain Considerations
  • Hardware Simulation Considerations
  • Software Programming Model
    • Software Files
    • Using the Performance Counter
    • Interrupt Behavior
  • Performance Counter API
    • PERF_RESET()
    • PERF_START_MEASURING()
    • PERF_STOP_MEASURING()
    • PERF_BEGIN()
    • PERF_END()
    • perf_print_formatted_report()
    • perf_get_total_time()
    • perf_get_section_time()
    • perf_get_num_starts()
    • alt_get_cpu_freq()
  • Document Revision History
• PLL Cores
  • Core Overview
  • Functional Description
    • ALTPLL Megafunction
    • Clock Outputs
    • PLL Status and Control Signals
    • System Reset Considerations
  • Instantiating the Avalon ALTPLL Core
  • Instantiating the PLL Core
  • Hardware Simulation Considerations
  • Register Definitions and Bit List
    • Status Register
    • Control Register
    • Phase Reconfig Control Register
  • Document Revision History
• Altera MSI to GIC Generator
  • Overview
  • Background
  • Feature Description
    • Interrupt Servicing Process
    • Registers of Component
      • Status Register
      • Error Register
      • Interrupt Mask Register
    • Unsupported Feature
  • Altera SMBus Core Interface
    • Component Interface
    • Component Parameterization
  • Document Revision History
• Altera Interrupt Latency Counter
  • Overview
  • Feature Description
    • Avalon-MM Compliant CSR Registers
      • Control Register
      • Frequency Register
      • Counter Stop Registers
      • Latency Data Registers
      • Data Valid Registers
    • 32-bit Counter
    • Interrupt Detector
  • Component Interface
  • Component Parameterization
  • Software Access
    • Routine for Level Sensitive Interrupts
    • Routine for Edge/Pulse Sensitive Interrupts
  • Implementation Details
    • Interrupt Latency Counter Architecture
  • IP Caveats
  • Document Revision History