Document Outline

• CPCI-6200
• Contents
• About this Manual
  • Overview of Contents
  • Abbreviations
  • Conventions
  • Summary of Changes
• Safety Notes
• Sicherheitshinweise
• Introduction
  • 1.1 Features
  • 1.2 Standard Compliances
  • 1.3 Mechanical Data
  • 1.4 Ordering Information
    • 1.4.1 Supported Board Models
    • 1.4.2 Board Accessories
  • 1.5 Product Identification
• Hardware Preparation and Installation
  • 2.1 Overview
  • 2.2 Unpacking the CPCI Baseboard
  • 2.3 Environmental Requirements
  • 2.4 Power Requirements
  • 2.5 Installing Accessories
    • 2.5.1 Installing a PMC Module on the CPCI Baseboard
    • 2.5.2 Installing the Rear Transition Module
  • 2.6 Preparing the Baseboard for Installation
    • 2.6.1 Inspecting the CPCI Baseboard
    • 2.6.2 Equipment Required for Installation
    • 2.6.3 Hardware Configuration
      • 2.6.3.1 Board Configuration Switch, S1
      • 2.6.3.2 IPMI Configuration Switch, S2
  • 2.7 Installing the CPCI Baseboard
  • 2.8 Removing the CPCI Baseboard
  • 2.9 Connecting to a Console Port
  • 2.10 Factory-Installed Linux
• Controls, LEDs, and Connectors
  • 3.1 Board Layout
  • 3.2 Front Panel
  • 3.3 Connectors and Headers
    • 3.3.1 CPCI Bus Connector, J1
    • 3.3.2 CPCI Bus Connector, J2
    • 3.3.3 CPCI User I/O Connector, J3
    • 3.3.4 CPCI Connector, J4
    • 3.3.5 CPCI User I/O Connector, J5
    • 3.3.6 PCI Mezzanine Card (PMC) Connectors
    • 3.3.7 Ethernet Connector
    • 3.3.8 USB Connector
    • 3.3.9 Serial Port Connector, J16
    • 3.3.10 Board Insertion/Extraction Connector, P1
    • 3.3.11 DDR3 SO-DIMM Connectors, XJ1 and XJ2
    • 3.3.12 PCI Express Expansion Connector, J17
    • 3.3.13 IPMI Debug and FW Programming Header, P3
    • 3.3.14 Processor Debug Header, P4
    • 3.3.15 Boundary Scan Header, P5
    • 3.3.16 Processor COP Header, P6
    • 3.3.17 PCI Express Switch Header, P7
  • 3.4 Switches
    • 3.4.1 Onboard Switches
    • 3.4.2 Reset/Abort Switch, P2
  • 3.5 Front Panel LEDs
  • 3.6 Status Indicators
• Functional Description
  • 4.1 Overview
  • 4.2 MPC8572 Integrated Processor
  • 4.3 I2C Serial Interface and Devices
    • 4.3.1 I2C Bus 0
    • 4.3.2 I2C Bus 1
    • 4.3.3 I2C Bus 2
    • 4.3.4 I2C Bus 3
    • 4.3.5 I2C Bus 4
    • 4.3.6 I2C Bus 5
  • 4.4 System Memory
  • 4.5 Timers
  • 4.6 Ethernet Interfaces
  • 4.7 Local Bus Interface
    • 4.7.1 Flash Memory
    • 4.7.2 MRAM (Magnetoresistive Random Access Memory)
    • 4.7.3 Control and Timers PLD
    • 4.7.4 Serial COM Ports
  • 4.8 DUART Interface
  • 4.9 PCI Express Port
  • 4.10 PCI/PCI-X Bus
    • 4.10.1 PCI Mezzanine Card Sites (PCI-X Bus 1 and 2)
    • 4.10.2 PCI 6466 Universal Bridge (PCI Bus 3)
    • 4.10.3 USB (PCI Bus 4)
    • 4.10.4 PCI Bus Frequency
  • 4.11 Operation Modes
    • 4.11.1 System Controller Mode
    • 4.11.2 Peripheral Mode
    • 4.11.3 Stand Alone Mode
  • 4.12 PCI Express Expansion
  • 4.13 System Interrupts
  • 4.14 Clock Distribution
  • 4.15 MPC8572 System Clock
  • 4.16 Reset Control Logic
    • 4.16.1 Abort/Reset Switch
    • 4.16.2 Reset Timing
  • 4.17 RTC Battery
  • 4.18 IPMI Controller
    • 4.18.1 Programming the IPMI Firmware
  • 4.19 Programmable Devices
    • 4.19.1 Local Bus Control CPLD
    • 4.19.2 Reset CPLD
    • 4.19.3 CPCI Control CPLD
    • 4.19.4 Serial Multiplexer CPLD
• Transition Module Preparation and Installation
  • 5.1 Overview
  • 5.2 Block Diagram
  • 5.3 Preparing the Transition Module
  • 5.4 Rear Panel Connectors
  • 5.5 On-Board Connectors and Headers
    • 5.5.1 IDE CompactFlash Connector
    • 5.5.2 PMC I/O Module Connectors
      • 5.5.2.1 Host IO Connectors
      • 5.5.2.2 PMC I/O Connectors
    • 5.5.3 CompactPCI User I/O Connector
    • 5.5.4 CompactPCI User I/O Connector
    • 5.5.5 10/100/1000BaseTx Connectors
    • 5.5.6 COM1 And COM2 Connectors (MXP Version)
    • 5.5.7 RJ-45 to DB-9 Adapter for COM1 to PC COM1
  • 5.6 Jumper Settings
    • 5.6.1 CompactFlash Jumper
    • 5.6.2 COM1 and COM2 Asynchronous Serial Ports Jumpers
  • 5.7 Functional Description
    • 5.7.1 IDE Flash
    • 5.7.2 Ethernet Interface (CompactPCI Version)
    • 5.7.3 Hot-Swap Support
    • 5.7.4 Serial EEPROM
    • 5.7.5 PMC I/O Modules
    • 5.7.6 Asynchronous Serial Ports
      • 5.7.6.1 I/O Signal Multiplexing (IOMX)
      • 5.7.6.2 Serial Port Redirection
      • 5.7.6.3 Asynchronous Serial Port Diagrams
      • 5.7.6.4 Port Configuration Diagrams
    • 5.7.7 PMC I/O Module
    • 5.7.8 PMC I/O Module Form Factor
    • 5.7.9 PMC I/O Connector
    • 5.7.10 Host I/O Connector
    • 5.7.11 PMC I/O Module Presence Detection and Identification
  • 5.8 Installing the PIM
  • 5.9 Installing the Transition Module
  • 5.10 Removing the Transition Module in a Hot-Swap Chassis
• MOTLoad Firmware
  • 6.1 Overview
  • 6.2 MOTLoad Description
  • 6.3 MOTLoad Implementation and Memory Requirements
  • 6.4 MOTLoad Commands
  • 6.5 MOTLoad Utility Applications
  • 6.6 MOTLoad Tests
  • 6.7 Using MOTLoad
    • 6.7.1 Command Line Interface
    • 6.7.2 Command Line Help
    • 6.7.3 Command Line Rules
  • 6.8 MOTLoad Command List
• Control via IPMI
  • 7.1 Standard IPMI Commands
    • 7.1.1 Global IPMI Commands
    • 7.1.2 Watchdog Commands
    • 7.1.3 IPMI Messaging Commands
    • 7.1.4 SEL Device Commands
    • 7.1.5 SDR Repository Commands
    • 7.1.6 FRU Inventory Commands
    • 7.1.7 Sensor Device Commands
    • 7.1.8 Chassis Device Commands
  • 7.2 PICMG 2.9 Commands
  • 7.3 Artesyn Specific Commands
    • 7.3.1 Firmware Upgrade Commands
      • 7.3.1.1 Start Firmware Upgrade
      • 7.3.1.2 Continue Firmware Upgrade
      • 7.3.1.3 Finish Firmware Upgrade
    • 7.3.2 OEM Commands
      • 7.3.2.1 BMC/PM Change Role
      • 7.3.2.2 Get Geographical Address
  • 7.4 FRU Information
  • 7.5 Sensor Description
• Memory Maps and Addresses
  • 8.1 Default Processor Memory Map
  • 8.2 CPCI-6200 Memory Map
  • 8.3 Local Bus Controller Memory Map
  • 8.4 System I/O Memory Map
    • 8.4.1 System Status Register
    • 8.4.2 System Control Register
    • 8.4.3 Front Panel LEDs Control and Status Register
    • 8.4.4 NOR Flash Control and Status Register
    • 8.4.5 Interrupt Register 1
    • 8.4.6 Interrupt Register 2
    • 8.4.7 Interrupt Mask Register
    • 8.4.8 Presence Detect Register
    • 8.4.9 NAND Flash Chip 1 Control Register
    • 8.4.10 NAND Flash Chip 1 Select Register
    • 8.4.11 NAND Flash Chip 1 Presence Register
    • 8.4.12 NAND Flash Chip 1 Status Register
    • 8.4.13 NAND Flash Chip 2 Control Register
    • 8.4.14 NAND Flash Chip 2 Select Register
    • 8.4.15 NAND Flash Chip 2 Presence Register
    • 8.4.16 NAND Flash Chip 2 Status Register
    • 8.4.17 CPCI Control and Status Register
    • 8.4.18 Geographic Address Read Register
    • 8.4.19 Watchdog Timer Load Register
    • 8.4.20 Watchdog Timer Control Register
    • 8.4.21 Watchdog Timer Resolution Register
    • 8.4.22 Watchdog Timer Count Register
    • 8.4.23 PLD Revision Register
    • 8.4.24 PLD Date Code Register
    • 8.4.25 Test Register 1
    • 8.4.26 Test Register 2
    • 8.4.27 External Timer Registers
      • 8.4.27.1 Prescaler Register
      • 8.4.27.2 Control Registers
      • 8.4.27.3 Compare Registers
      • 8.4.27.4 Counter Registers
  • 8.5 Interrupt Controller
  • 8.6 I2C Device Addresses
  • 8.7 PCI/PCI-X Configuration
    • 8.7.1 PCI IDSEL and Interrupt Assignment
    • 8.7.2 PCI Vendor and Device IDs
    • 8.7.3 PCI Arbitration Assignments
• A Replacing the Battery
  • A.1 Battery Location
  • A.2 Replacing the Battery
• B Related Documentation
  • B.1 Artesyn Embedded Technologies - Embedded Computing Documentation
  • B.2 Manufacturer’s Publications
  • B.3 Related Specifications