Artesyn CPCI-6200 Installation and Use (May 2015) User Manual
Cpci-6200
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Table of contents
Document Outline
- CPCI-6200
- Contents
- About this Manual
- Safety Notes
- Sicherheitshinweise
- Introduction
- Hardware Preparation and Installation
- Controls, LEDs, and Connectors
- 3.1 Board Layout
- 3.2 Front Panel
- 3.3 Connectors and Headers
- 3.3.1 CPCI Bus Connector, J1
- 3.3.2 CPCI Bus Connector, J2
- 3.3.3 CPCI User I/O Connector, J3
- 3.3.4 CPCI Connector, J4
- 3.3.5 CPCI User I/O Connector, J5
- 3.3.6 PCI Mezzanine Card (PMC) Connectors
- 3.3.7 Ethernet Connector
- 3.3.8 USB Connector
- 3.3.9 Serial Port Connector, J16
- 3.3.10 Board Insertion/Extraction Connector, P1
- 3.3.11 DDR3 SO-DIMM Connectors, XJ1 and XJ2
- 3.3.12 PCI Express Expansion Connector, J17
- 3.3.13 IPMI Debug and FW Programming Header, P3
- 3.3.14 Processor Debug Header, P4
- 3.3.15 Boundary Scan Header, P5
- 3.3.16 Processor COP Header, P6
- 3.3.17 PCI Express Switch Header, P7
- 3.4 Switches
- 3.5 Front Panel LEDs
- 3.6 Status Indicators
- Functional Description
- 4.1 Overview
- 4.2 MPC8572 Integrated Processor
- 4.3 I2C Serial Interface and Devices
- 4.4 System Memory
- 4.5 Timers
- 4.6 Ethernet Interfaces
- 4.7 Local Bus Interface
- 4.8 DUART Interface
- 4.9 PCI Express Port
- 4.10 PCI/PCI-X Bus
- 4.11 Operation Modes
- 4.12 PCI Express Expansion
- 4.13 System Interrupts
- 4.14 Clock Distribution
- 4.15 MPC8572 System Clock
- 4.16 Reset Control Logic
- 4.17 RTC Battery
- 4.18 IPMI Controller
- 4.19 Programmable Devices
- Transition Module Preparation and Installation
- 5.1 Overview
- 5.2 Block Diagram
- 5.3 Preparing the Transition Module
- 5.4 Rear Panel Connectors
- 5.5 On-Board Connectors and Headers
- 5.6 Jumper Settings
- 5.7 Functional Description
- 5.7.1 IDE Flash
- 5.7.2 Ethernet Interface (CompactPCI Version)
- 5.7.3 Hot-Swap Support
- 5.7.4 Serial EEPROM
- 5.7.5 PMC I/O Modules
- 5.7.6 Asynchronous Serial Ports
- 5.7.7 PMC I/O Module
- 5.7.8 PMC I/O Module Form Factor
- 5.7.9 PMC I/O Connector
- 5.7.10 Host I/O Connector
- 5.7.11 PMC I/O Module Presence Detection and Identification
- 5.8 Installing the PIM
- 5.9 Installing the Transition Module
- 5.10 Removing the Transition Module in a Hot-Swap Chassis
- MOTLoad Firmware
- Control via IPMI
- Memory Maps and Addresses
- 8.1 Default Processor Memory Map
- 8.2 CPCI-6200 Memory Map
- 8.3 Local Bus Controller Memory Map
- 8.4 System I/O Memory Map
- 8.4.1 System Status Register
- 8.4.2 System Control Register
- 8.4.3 Front Panel LEDs Control and Status Register
- 8.4.4 NOR Flash Control and Status Register
- 8.4.5 Interrupt Register 1
- 8.4.6 Interrupt Register 2
- 8.4.7 Interrupt Mask Register
- 8.4.8 Presence Detect Register
- 8.4.9 NAND Flash Chip 1 Control Register
- 8.4.10 NAND Flash Chip 1 Select Register
- 8.4.11 NAND Flash Chip 1 Presence Register
- 8.4.12 NAND Flash Chip 1 Status Register
- 8.4.13 NAND Flash Chip 2 Control Register
- 8.4.14 NAND Flash Chip 2 Select Register
- 8.4.15 NAND Flash Chip 2 Presence Register
- 8.4.16 NAND Flash Chip 2 Status Register
- 8.4.17 CPCI Control and Status Register
- 8.4.18 Geographic Address Read Register
- 8.4.19 Watchdog Timer Load Register
- 8.4.20 Watchdog Timer Control Register
- 8.4.21 Watchdog Timer Resolution Register
- 8.4.22 Watchdog Timer Count Register
- 8.4.23 PLD Revision Register
- 8.4.24 PLD Date Code Register
- 8.4.25 Test Register 1
- 8.4.26 Test Register 2
- 8.4.27 External Timer Registers
- 8.5 Interrupt Controller
- 8.6 I2C Device Addresses
- 8.7 PCI/PCI-X Configuration
- A Replacing the Battery
- B Related Documentation