Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 211)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 211
8.4.19 Watchdog Timer Load Register
LOAD—Counter Load; When the pattern 0xDB is written, the watchdog counter is loaded with
the count value.
1 RSVD R 0
0 RSVD R 0
Table 8-40 Geographic Address Read Register Field Definition
GA[4:0] Geographic Address Bits from Backplane. The value will depend
upon the chassis slot used for the board.
RSVD Reserved
Table 8-39 Geographic Address Read Register, 0xF200_0019 (continued)
Bit Field Operation Reset
Table 8-41 Watchdog Timer Load Register, 0xF200_0020
Bit Field Operation Reset
7 LOAD Write only, read returns zero 0x0
6
5
4
3
2
1
0