Document Outline

• Chapter1 Introduction
• 1.1 General Description
  • Figure1.1 Typical LSI53C1000R Board Application
  • Figure1.2 Typical LSI53C1000R System Application
• 1.2 Benefits of Ultra160 SCSI
• 1.3 Benefits of SURElink (Ultra160 SCSI Domain Validation) Technology
• 1.4 Benefits of LVDlink Technology
• 1.5 Benefits of TolerANT® Technology
• 1.6 Summary of LSI53C1000R Benefits
  • 1.6.1 SCSI Performance
  • 1.6.2 PCI Performance
  • 1.6.3 Integration
  • 1.6.4 Ease of Use
  • 1.6.5 Flexibility
  • 1.6.6 Reliability
  • 1.6.7 Testability
• Chapter2 Functional Description
  • Figure2.1 LSI53C1000R Block Diagram
• 2.1 PCI Functional Description
  • 2.1.1 PCI Addressing
  • 2.1.2 PCI Bus Commands and Functions Supported
    • Table 2.1 PCI Bus Commands and Encoding Types
  • 2.1.3 PCI Cache Mode
    • Table 2.2 PCI Cache Mode Alignment
• 2.2 SCSI Functional Description
  • 2.2.1 SCRIPTS Processor
  • 2.2.2 Internal SCRIPTS RAM
  • 2.2.3 64Bit Addressing in SCRIPTS
  • 2.2.4 Hardware Control of SCSI Activity LED
  • 2.2.5 Designing an Ultra160 SCSI System
    • Table 2.3 New Phases on SCSI Bus
  • 2.2.6 Prefetching SCRIPTS Instructions
  • 2.2.7 Opcode Fetch Burst Capability
  • 2.2.8 Load and Store Instructions
  • 2.2.9 JTAG Boundary Scan Testing
  • 2.2.10 Parity/CRC/AIP Options
    • Table 2.4 Bits Used for Parity/CRC/AIP Control and Generation
    • Table 2.5 SCSI Parity Errors and Interrupts
  • 2.2.11 DMA FIFO
    • Figure2.2 DMA FIFO Sections
  • 2.2.12 SCSI Data Paths
    • Figure2.3 LSI53C1000R Host Interface SCSI Data Paths
  • 2.2.13 SCSI Bus Interface
    • Figure2.4 Regulated Termination for Ultra160 SCSI
  • 2.2.14 Select/Reselect during Selection/Reselection
  • 2.2.15 Synchronous Operation
    • Table 2.6 SCF Divisor Values
    • Figure2.5 Determining the Synchronous Transfer Rate
  • 2.2.16 Interrupt Handling
  • 2.2.17 Interrupt Routing
    • Figure2.6 Interrupt Routing Hardware Using the LSI53C1000R
  • 2.2.18 Chained Block Moves
    • Figure2.7 Block Move and Chained Block Move Instructions
• 2.3 Parallel ROM Interface
  • Table 2.7 Parallel ROM Support
• 2.4 Serial EEPROM Interface
  • 2.4.1 Default Download Mode
    • Table 2.8 Default Download Mode Serial EEPROM Data Format
  • 2.4.2 No Download Mode
• 2.5 Power Management
  • Table 2.9 Power States
  • 2.5.1 Power State D0
  • 2.5.2 Power State D1
  • 2.5.3 Power State D2
  • 2.5.4 Power State D3
• Chapter3 Signal Descriptions
• 3.1 Signal Organization
  • Figure3.1 LSI53C1000R Signal Grouping
• 3.2 Internal Pull-ups and Pull-downs
  • Table 3.1 LSI53C1000R Internal Pull-ups and Pull-downs
• 3.3 PCI Bus Interface Signals
  • 3.3.1 System Signals
    • Table 3.2 System Signals
  • 3.3.2 Address and Data Signals
    • Table 3.3 Address and Data Signals
  • 3.3.3 Interface Control Signals
    • Table 3.4 Interface Control Signals
  • 3.3.4 Arbitration Signals
    • Table 3.5 Arbitration Signals
  • 3.3.5 Error Reporting Signals
    • Table 3.6 Error Reporting Signals
  • 3.3.6 Interrupt Signals
    • Table 3.7 Interrupt Signals
• 3.4 SCSI Bus Interface Signals
  • Table 3.8 SCSI Bus Interface Signals
  • Table 3.9 SCSI Signals
  • Table 3.10 SCSI Control Signals
• 3.5 General Purpose I/O (GPIO) Signals
  • Table 3.11 GPIO Signals
• 3.6 Flash ROM and Memory Interface Signals
  • Table 3.12 Flash ROM and Memory Interface Signals
• 3.7 Test Interface Signals
  • Table 3.13 Test Interface Signals
• 3.8 Power and Ground Signals
  • Table 3.14 Power and Ground Signals
• 3.9 MAD Bus Programming
  • Table 3.15 MAD[3:1] Pin Decoding
• Chapter4 Registers
• 4.1 PCI Configuration Registers
  • Table 4.1 PCI Configuration Register Map
• 4.2 SCSI Registers
  • Table 4.2 SCSI Register Map
  • Table 4.3 Maximum Synchronous Offset
  • Figure4.1 Single Transition Transfer Waveforms
  • Figure4.2 DT Transfer Waveforms (XCLKS Examples)
  • Figure4.3 DT Transfer Waveforms (XCLKH Examples)
  • Table 4.4 DT Transfer Rates
  • Table 4.5 Single Transition Transfer Rates
• 4.3 SCSI Shadow Registers
• Chapter5 SCSI SCRIPTS Instruction Set
• 5.1 SCSI SCRIPTS
  • Figure5.1 SCRIPTS Overview
• 5.2 Block Move Instructions
  • 5.2.1 First Dword
    • Figure5.2 Block Move Instruction – First Dword
  • 5.2.2 Second Dword
    • Figure5.3 Block Move Instruction – Second Dword
  • 5.2.3 Third Dword
    • Figure5.4 Block Move Instruction – Third Dword
• 5.3 I/O Instructions
  • 5.3.1 First Dword
    • Figure5.5 First 32Bit Word of the I/O Instruction
  • 5.3.2 Second Dword
    • Figure5.6 Second 32Bit Word of the I/O Instruction
• 5.4 Read/Write Instructions
  • 5.4.1 First Dword
    • Figure5.7 Read/Write Instruction – First Dword
  • 5.4.2 Second Dword
    • Figure5.8 Read/Write Instruction – Second Dword
  • 5.4.3 Read-Modify-Write Cycles
  • 5.4.4 Move to/from SFBR Cycles
    • Table 5.1 Read/Write Instructions
• 5.5 Transfer Control Instructions
  • 5.5.1 First Dword
    • Figure5.9 Transfer Control Instructions – First Dword
  • 5.5.2 Second Dword
    • Figure5.10 Transfer Control Instructions – Second Dword
  • 5.5.3 Third Dword
    • Figure5.11 Transfer Control Instructions – Third Dword
• 5.6 Memory Move Instructions
  • Figure5.12 Memory Move Instructions – First Dword
  • 5.6.1 Read/Write System Memory from a SCRIPT
  • 5.6.2 Second Dword
    • Figure5.13 Memory Move Instructions – Second Dword
  • 5.6.3 Third Dword
    • Figure5.14 Memory Move Instructions – Third Dword
• 5.7 Load and Store Instructions
  • 5.7.1 First Dword
    • Figure5.15 Load and Store Instruction – First Dword
  • 5.7.2 Second Dword
    • Figure5.16 Load and Store Instructions – Second Dword
• Chapter6 Specifications
• 6.1 DC Characteristics
  • Table 6.1 Absolute Maximum Stress Ratings
  • Table 6.2 Operating Conditions
  • Table 6.3 LVD Driver SCSI Signals – SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, S...
  • Figure6.1 LVD Driver
  • Table 6.4 LVD Receiver SCSI Signals – SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/,...
  • Figure6.2 LVD Receiver
  • Table 6.5 DIFFSENS SCSI Signals
  • Table 6.6 Input Capacitance
  • Table 6.7 8 mA Bidirectional Signals – GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4
  • Table 6.8 4 mA Bidirectional Signals – MAD[7:0]
  • Table 6.9 4 mA Output Signals – MAS[1:0]/, MCE/, MOE/_TESTOUT, MWE/, TDO
  • Table 6.10 8 mA PCI Bidirectional Signals – AD[63:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, ...
  • Table 6.11 Input Signals – CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TMS
  • Table 6.12 8 mA Output Signals – INTA/, INTB/, ALT_INTA/, ALT_INTB/, REQ/, SERR/
• 6.2 TolerANT Technology Electrical Characteristics
  • Table 6.13 TolerANT Technology Electrical Characteristics for SE SCSI Signals
  • Figure6.3 Rise and Fall Time Test Condition
  • Figure6.4 SCSI Input Filtering
  • Figure6.5 Hysteresis of SCSI Receivers
  • Figure6.6 Input Current as a Function of Input Voltage
  • Figure6.7 Output Current as a Function of Output Voltage
• 6.3 AC Characteristics
  • Table 6.14 External Clock
  • Figure6.8 External Clock
  • Table 6.15 Reset Input
  • Figure6.9 Reset Input
  • Table 6.16 Interrupt Output
  • Figure6.10 Interrupt Output
• 6.4 PCI and External Memory Interface Timing Diagrams
  • 6.4.1 Target Timing
    • Table 6.17 PCI Configuration Register Read
    • Figure6.11 PCI Configuration Register Read
    • Table 6.18 PCI Configuration Register Write
    • Figure6.12 PCI Configuration Register Write
    • Table 6.19 Operating Register/SCRIPTS RAM Read, 32 Bits
    • Figure6.13 Operating Registers/SCRIPTS RAM Read, 32 Bits
    • Table 6.20 Operating Register/SCRIPTS RAM Read, 64 Bits
    • Figure6.14 Operating Register/SCRIPTS RAM Read, 64 Bits
    • Table 6.21 Operating Register/SCRIPTS RAM Read, 32 Bits
    • Figure6.15 Operating Register/SCRIPTS RAM Read, 32 Bits
    • Table 6.22 Operating Register/SCRIPTS RAM Write, 64 Bits
    • Figure6.16 Operating Register/SCRIPTS RAM Write, 64 Bits
  • 6.4.2 Initiator Timing
    • Table 6.23 Nonburst Opcode Fetch, 32-Bit Address and Data
    • Figure6.17 Nonburst Opcode Fetch, 32-Bit Address and Data
    • Table 6.24 Burst Opcode Fetch, 32-Bit Address and Data
    • Figure6.18 Burst Opcode Fetch, 32-Bit Address and Data
    • Table 6.25 Back to Back Read, 32-Bit Address and Data
    • Figure6.19 Back to Back Read, 32-Bit Address and Data
    • Table 6.26 Back to Back Write, 32-Bit Address and Data
    • Figure6.20 Back to Back Write, 32-Bit Address and Data
    • Table 6.27 Burst Read, 32-Bit Address and Data
    • Figure6.21 Burst Read, 32-Bit Address and Data
    • Table 6.28 Burst Read, 64-Bit Address and Data
    • Figure6.22 Burst Read, 64-Bit Address and Data
    • Table 6.29 Burst Write, 32-Bit Address and Data
    • Figure6.23 Burst Write, 32-Bit Address and Data
    • Table 6.30 Burst Write, 64-Bit Address and Data
    • Figure6.24 Burst Write, 64-Bit Address and Data
  • 6.4.3 External Memory Timing
    • Table 6.31 External Memory Read
    • Figure6.25 External Memory Read
    • Table 6.32 External Memory Write
    • Figure6.26 External Memory Write
    • Table 6.33 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle
    • Figure6.27 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle
    • Table 6.34 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle
    • Figure6.28 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle
    • Figure6.29 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Read Cycle
    • Figure6.30 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Write Cycle
    • Table 6.35 Slow Memory (³ 128 Kbytes) Read Cycle
    • Figure6.31 Slow Memory (³ 128 Kbytes) Read Cycle
    • Table 6.36 Slow Memory (³ 128 Kbytes) Write Cycle
    • Figure6.32 Slow Memory (³ 128 Kbytes) Write Cycle
    • Table 6.37 £ 64 Kbytes ROM Read Cycle
    • Figure6.33 £ 64 Kbytes ROM Read Cycle
    • Table 6.38 £ 64 Kbytes ROM Write Cycle
    • Figure6.34 £ 64 Kbytes ROM Write Cycle
• 6.5 SCSI Timing Diagrams
  • Table 6.39 Initiator Asynchronous Send
  • Figure6.35 Initiator Asynchronous Send
  • Table 6.40 Initiator Asynchronous Receive
  • Figure6.36 Initiator Asynchronous Receive
  • Table 6.41 Target Asynchronous Send
  • Figure6.37 Target Asynchronous Send
  • Table 6.42 Target Asynchronous Receive
  • Figure6.38 Target Asynchronous Receive
  • Table 6.43 SCSI-1 Transfers (SE 5.0 Mbytes)
  • Table 6.44 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
  • Table 6.45 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers...
  • Table 6.46 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Qu...
  • Figure6.39 Initiator and Target ST Synchronous Transfer
  • Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
  • Table 6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers...
  • Table 6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Qu...
  • Table 6.50 Ultra160 SCSI Transfers 160 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock
  • Figure6.40 Initiator and Target DT Synchronous Transfer
• 6.6 Package Drawings
  • Figure6.41 LSI53C1000R 456 BGA Chip – Top View
  • Table 6.51 Alphanumeric List by Signal Name
  • Table 6.52 Alphanumeric List by BGA Position
  • Figure6.42 LSI53C1000R 456 BGA Mechanical Drawing
• AppendixA Register Summary
  • TableA.1 LSI53C1000R PCI Register Map
  • TableA.2 LSI53C1000R SCSI Register Map
• AppendixB External Memory Interface Diagram Examples
  • FigureB.1 16 Kbyte Interface with 200 ns Memory
  • FigureB.2 64 Kbyte Interface with 150 ns Memory
  • FigureB.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Memory
  • FigureB.4 512 Kbyte Interface with 150 ns Memory
• Index
• Customer Feedback