Document Outline

• 1. Pin Description
• 2. Typical Connection Diagram
  • Figure 1. Typical Connection Diagram
• 3. Characteristics and Specifications
  • Recommended Operating Conditions
  • Absolute Maximum Ratings
  • DC Electrical Characteristics
  • AC Electrical Characteristics
  • PLL Performance Plots
    • Figure 2. CLK_IN Sinusoidal Jitter Tolerance
    • Figure 3. CLK_IN Sinusoidal Jitter Transfer
    • Figure 4. CLK_IN Random Jitter Rejection and Tolerance
• 4. Architecture Overview
  • 4.1 Delta-Sigma Fractional-N Frequency Synthesizer
    • Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer
  • 4.2 Hybrid Analog-Digital Phase Locked Loop
    • Figure 6. Hybrid Analog-Digital PLL
    • 4.2.1 Fractional-N Source Selection for the Frequency Synthesizer
      • Figure 7. Fractional-N Source Selection Overview
• 5. Applications
  • 5.1 One Time Programmability
    • Table 1. Modal and Global Configuration
  • 5.2 Timing Reference Clock Input
    • 5.2.1 Internal Timing Reference Clock Divider
      • Figure 8. Internal Timing Reference Clock Divider
      • Figure 9. REF_CLK Frequency vs. a Fixed CLK_OUT
    • 5.2.2 Crystal Connections (XTI and XTO)
      • Figure 10. External Component Requirements for Crystal Circuit
    • 5.2.3 External Reference Clock (REF_CLK)
  • 5.3 Frequency Reference Clock Input, CLK_IN
    • 5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN
      • Figure 11. Low bandwidth and new clock domain
      • Figure 12. High bandwidth with CLK_IN domain re-use
  • 5.4 Output to Input Frequency Ratio Configuration
    • 5.4.1 User Defined Ratio (RUD), Frequency Synthesizer Mode
    • 5.4.2 User Defined Ratio (RUD), Hybrid PLL Mode
    • 5.4.3 Ratio Modifier (R-Mod)
      • Table 2. Ratio Modifier
    • 5.4.4 Effective Ratio (REFF)
    • 5.4.5 Fractional-N Source Selection
    • 5.4.6 Ratio Configuration Summary
      • Figure 13. Ratio Feature Summary
  • 5.5 PLL Clock Output
    • Figure 14. PLL Clock Output Options
  • 5.6 Auxiliary Output
    • Figure 15. Auxiliary Output Selection
  • 5.7 Mode Pin Functionality
    • 5.7.1 M1 and M0 Mode Pin Functionality
    • 5.7.2 M2 Mode Pin Functionality
      • Figure 16. M2 Mapping Options
  • 5.8 Clock Output Stability Considerations
    • 5.8.1 Output Switching
    • 5.8.2 PLL Unlock Conditions
  • 5.9 Required Power Up Sequencing for Programmed Devices
• 6. Parameter Descriptions
  • Figure 17. Parameter Configuration Sets
  • 6.1 Modal Configuration Sets
    • 6.1.1 R-Mod Selection (RModSel[1:0])
    • 6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0])
    • 6.1.3 Lock Clock Ratio (LockClk[1:0])
    • 6.1.4 Fractional-N Source for Frequency Synthesizer (FracNSrc)
  • 6.2 Ratio 0 - 3
  • 6.3 Global Configuration Parameters
    • 6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg)
    • 6.3.2 Reference Clock Input Divider (RefClkDiv[1:0])
    • 6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl)
    • 6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg)
    • 6.3.5 M2 Pin Configuration (M2Config[2:0])
    • 6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0])
• 7. Calculating the User Defined Ratio
  • 7.1 High Resolution 12.20 Format
    • Table 3. Example 12.20 R-Values
  • 7.2 High Multiplication 20.12 Format
    • Table 4. Example 20.12 R-Values
• 8. Programming Information
• 9. Package Dimensions
  • Thermal Characteristics
• 10. Ordering Information
• 11. Revision History