Document Outline

• 1. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • Analog Input Characteristics
  • A/D Digital Filter Characteristics
  • Analog Output Characteristics
  • D/A Digital Filter Characteristics
  • Switching Characteristics
    • Figure 1. Serial Audio Port Master Mode Timing
    • Figure 2. Serial Audio Port Slave Mode Timing
  • Switching Characteristics - Control Port - I²C™ Format
    • Figure 3. Control Port Timing - I²C Format
  • Switching Characteristics - Control Port - SPI™ Format
    • Figure 4. Control Port Timing - SPI Format
  • DC Electrical Characteristics
  • Digital Interface Characteristics
• 2. Pin Descriptions
• 3. Typical Connection Diagram
  • Figure 5. Typical Connection Diagram
• 4. Applications
  • 4.1 Overview
  • 4.2 Analog Inputs
    • 4.2.1 Line-Level Inputs
      • Figure 6. Full-Scale Analog Input
    • 4.2.2 High-Pass Filter and DC Offset Calibration
  • 4.3 Analog Outputs
    • 4.3.1 Line-Level Outputs and Filtering
      • Figure 7. Full-Scale Output
    • 4.3.2 Interpolation Filter
    • 4.3.3 Digital Volume and Mute Control
    • 4.3.4 ATAPI Specification
      • Figure 8. ATAPI Block Diagram (x = channel pair 1, 2, or 3)
  • 4.4 S/PDIF Receiver
    • 4.4.1 8:2 S/PDIF Input Multiplexer
    • 4.4.2 Error Reporting and Hold Function
    • 4.4.3 Channel Status Data Handling
    • 4.4.4 User Data Handling
    • 4.4.5 Non-Audio Auto-Detection
  • 4.5 Clock Generation
    • Figure 9. CS42526 Clock Generation
    • 4.5.1 PLL and Jitter Attenuation
    • 4.5.2 OMCK System Clock Mode
      • Table 1. Common OMCK Clock Frequencies
    • 4.5.3 Master Mode
      • Table 2. Common PLL Output Clock Frequencies
    • 4.5.4 Slave Mode
      • Table 3. Slave Mode Clock Ratios
  • 4.6 Digital Interfaces
    • 4.6.1 Serial Audio Interface Signals
      • Table 4. Serial Audio Port Channel Allocations
    • 4.6.2 Serial Audio Interface Formats
      • Figure 10. I²S Serial Audio Formats
      • Figure 11. Left-Justified Serial Audio Formats
      • Figure 12. Right-Justified Serial Audio Formats
      • Figure 13. One Line Mode #1 Serial Audio Format
      • Figure 14. One Line Mode #2 Serial Audio Format
    • 4.6.3 ADCIN1/ADCIN2 Serial Data Format
      • Figure 15. ADCIN1/ADCIN2 Serial Audio Format
    • 4.6.4 One-Line Mode (OLM) Configurations
      • Figure 16. OLM Configuration #1
      • Figure 17. OLM Configuration #2
      • Figure 18. OLM Configuration #3
      • Figure 19. OLM Configuration #4
      • Figure 20. OLM Configuration #5
  • 4.7 Control Port Description and Timing
    • 4.7.1 SPI Mode
      • Figure 21. Control Port Timing in SPI Mode
    • 4.7.2 I²C Mode
      • Figure 22. Control Port Timing, I²C Write
      • Figure 23. Control Port Timing, I²C Read
  • 4.8 Interrupts
  • 4.9 Reset and Power-Up
  • 4.10 Power Supply, Grounding, and PCB Layout
• 5. Register Quick Reference
• 6. Register Description
  • Table 5. DAC De-Emphasis
  • Table 6. Receiver De-Emphasis
  • Table 7. Digital Interface Formats
  • Table 8. ADC One-Line Mode
  • Table 9. DAC One-Line Mode
  • Table 10. RMCK Divider Settings
  • Table 11. OMCK Frequency Settings
  • Table 12. Master Clock Source Select
  • Table 13. AES Format Detection
  • Table 14. Receiver Clock Frequency Detection
  • Table 15. Example Digital Volume Settings
  • Table 16. ATAPI Decode
  • Table 17. Example ADC Input Gain Settings
  • Table 18. TXP Output Selection
  • Table 19. Receiver Input Selection
  • Table 20. Auxiliary Data Width Selection
• 7. Parameter Definitions
• 8. Appendix A: External Filters
  • 8.1 ADC Input Filter
    • Figure 24. Recommended Analog Input Buffer
  • 8.2 DAC Output Filter
    • Figure 25. Recommended Analog Output Buffer
• 9. Appendix B: S/PDIF Receiver
  • 9.1 Error Reporting and Hold Function
  • 9.2 Channel Status Data Handling
    • Figure 26. Channel Status Data Buffer Structure
    • 9.2.1 Channel Status Data E Buffer Access
    • 9.2.2 Serial Copy Management System (SCMS)
  • 9.3 User (U) Data E Buffer Access
    • 9.3.1 Non-Audio Auto-Detection
• 10. Appendix C: PLL Filter
  • Figure 27. PLL Block Diagram
  • 10.1 External Filter Components
    • 10.1.1 General
      • Table 21. External PLL Component Values & Locking Modes
    • 10.1.2 Jitter Attenuation
      • Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2
      • Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3
    • 10.1.3 Capacitor Selection
    • 10.1.4 Circuit Board Layout
      • Figure 30. Recommended Layout Example
• 11. Appendix D: External AES3-S/PDIF-IEC60958 Receiver Components
  • 11.1 AES3 Receiver External Components
    • Figure 31. Consumer Input Circuit
    • Figure 32. S/PDIF MUX Input Circuit
    • Figure 33. TTL/CMOS Input Circuit
• 12. Appendix E: ADC Filter Plots
  • Figure 34. Single-Speed Mode Stopband Rejection
  • Figure 35. Single-Speed Mode Transition Band
  • Figure 36. Single-Speed Mode Transition Band (Detail)
  • Figure 37. Single-Speed Mode Passband Ripple
  • Figure 38. Double-Speed Mode Stopband Rejection
  • Figure 39. Double-Speed Mode Transition Band
  • Figure 40. Double-Speed Mode Transition Band (Detail)
  • Figure 41. Double-Speed Mode Passband Ripple
  • Figure 42. Quad-Speed Mode Stopband Rejection
  • Figure 43. Quad-Speed Mode Transition Band
  • Figure 44. Quad-Speed Mode Transition Band (Detail)
  • Figure 45. Quad-Speed Mode Passband Ripple
• 13. Appendix F: DAC Filter Plots
  • Figure 46. Single-Speed (fast) Stopband Rejection
  • Figure 47. Single-Speed (fast) Transition Band
  • Figure 48. Single-Speed (fast) Transition Band (detail)
  • Figure 49. Single-Speed (fast) Passband Ripple
  • Figure 50. Single-Speed (slow) Stopband Rejection
  • Figure 51. Single-Speed (slow) Transition Band
  • Figure 52. Single-Speed (slow) Transition Band (detail)
  • Figure 53. Single-Speed (slow) Passband Ripple
  • Figure 54. Double-Speed (fast) Stopband Rejection
  • Figure 55. Double-Speed (fast) Transition Band
  • Figure 56. Double-Speed (fast) Transition Band (detail)
  • Figure 57. Double-Speed (fast) Passband Ripple
  • Figure 58. Double-Speed (slow) Stopband Rejection
  • Figure 59. Double-Speed (slow) Transition Band
  • Figure 60. Double-Speed (slow) Transition Band (detail)
  • Figure 61. Double-Speed (slow) Passband Ripple
  • Figure 62. Quad-Speed (fast) Stopband Rejection
  • Figure 63. Quad-Speed (fast) Transition Band
  • Figure 64. Quad-Speed (fast) Transition Band (detail)
  • Figure 65. Quad-Speed (fast) Passband Ripple
  • Figure 66. Quad-Speed (slow) Stopband Rejection
  • Figure 67. Quad-Speed (slow) Transition Band
  • Figure 68. Quad-Speed (slow) Transition Band (detail)
  • Figure 69. Quad-Speed (slow) Passband Ripple
• 14. Package Dimensions
  • Thermal Characteristics
• 15. Ordering Information
• 16. References
• 17. Revision History