Table 10. rmck divider settings, Table 11. omck frequency settings, 7 clock control (address 06h) – Cirrus Logic CS42526 User Manual
Page 52: The pll will lock to, Clock con
52
DS585F2
CS42526
6.7
Clock Control (address 06h)
6.7.1
RMCK DIVIDE (RMCK_DIVX)
Default = 00
Function:
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
6.7.2
OMCK FREQUENCY (OMCK FREQX)
Default = 00
Function:
Sets the appropriate frequency for the supplied OMCK.
6.7.3
PLL LOCK TO LRCK (PLL_LRCK)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, the internal PLL of the CS42526 will lock to the SAI_LRCK of the SAI serial port.
7
6
5
4
3
2
1
0
RMCK_DIV1
RMCK_DIV0
OMCK Freq1 OMCK Freq0
PLL_LRCK
SW_CTRL1
SW_CTRL0
FRC_PLL_LK
RMCK_DIV1 RMCK_DIV0
Description
0
0
Divide by 1
0
1
Divide by 2
1
0
Divide by 4
1
1
Multiply by 2
Table 10. RMCK Divider Settings
OMCK Freq1 OMCK Freq0
Description
0
0
11.2896 MHz or 12.2880 MHz
0
1
16.9344 MHz or 18.4320 MHz
1
0
22.5792 MHz or 24.5760 MHz
1
1
Reserved
Table 11. OMCK Frequency Settings