Cirrus Logic CS42526 - Manual (Page 4)

4 DS585F2
CS42526
11. APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS .......................... 82
11.1 AES3 Receiver External Components .......................................................................................... 82
12. APPENDIX E: ADC FILTER PLOTS .................................................................................................. 83
13. APPENDIX F: DAC FILTER PLOTS .................................................................................................. 85
14. PACKAGE DIMENSIONS ............................................................................................................... 89
THERMAL CHARACTERISTICS .......................................................................................................... 89
15. ORDERING INFORMATION .............................................................................................................. 90
16. REFERENCES .................................................................................................................................... 90
17. REVISION HISTORY ......................................................................................................................... 91
LIST OF FIGURES
Figure 1. Serial Audio Port Master Mode Timing ...................................................................................... 11
Figure 2. Serial Audio Port Slave Mode Timing ........................................................................................ 11
Figure 3. Control Port Timing - I²C Format ................................................................................................ 12
Figure 4. Control Port Timing - SPI Format ............................................................................................... 13
Figure 5. Typical Connection Diagram ...................................................................................................... 19
Figure 6. Full-Scale Analog Input .............................................................................................................. 20
Figure 7. Full-Scale Output ....................................................................................................................... 21
Figure 8. ATAPI Block Diagram (x = channel pair 1, 2, or 3) .................................................................... 22
Figure 9. CS42526 Clock Generation ....................................................................................................... 24
Figure 10. I²S Serial Audio Formats .......................................................................................................... 28
Figure 11. Left-Justified Serial Audio Formats .......................................................................................... 29
Figure 12. Right-Justified Serial Audio Formats ........................................................................................ 29
Figure 13. One Line Mode #1 Serial Audio Format ................................................................................... 30
Figure 14. One Line Mode #2 Serial Audio Format ................................................................................... 30
Figure 15. ADCIN1/ADCIN2 Serial Audio Format ..................................................................................... 31
Figure 16. OLM Configuration #1 .............................................................................................................. 32
Figure 17. OLM Configuration #2 .............................................................................................................. 33
Figure 18. OLM Configuration #3 .............................................................................................................. 34
Figure 19. OLM Configuration #4 .............................................................................................................. 35
Figure 20. OLM Configuration #5 .............................................................................................................. 36
Figure 21. Control Port Timing in SPI Mode ............................................................................................. 37
Figure 22. Control Port Timing, I²C Write .................................................................................................. 38
Figure 23. Control Port Timing, I²C Read .................................................................................................. 38
Figure 24. Recommended Analog Input Buffer ......................................................................................... 73
Figure 25. Recommended Analog Output Buffer ...................................................................................... 73
Figure 26. Channel Status Data Buffer Structure ...................................................................................... 75
Figure 27. PLL Block Diagram .................................................................................................................. 77
Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2 .............................................. 79
Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3 ...................................................... 79
Figure 30. Recommended Layout Example .............................................................................................. 81
Figure 31. Consumer Input Circuit ............................................................................................................ 82
Figure 32. S/PDIF MUX Input Circuit ........................................................................................................ 82
Figure 33. TTL/CMOS Input Circuit ........................................................................................................... 82
Figure 34. Single-Speed Mode Stopband Rejection ................................................................................. 83
Figure 35. Single-Speed Mode Transition Band ....................................................................................... 83
Figure 36. Single-Speed Mode Transition Band (Detail) ........................................................................... 83
Figure 37. Single-Speed Mode Passband Ripple ..................................................................................... 83
Figure 38. Double-Speed Mode Stopband Rejection ................................................................................ 83
Figure 39. Double-Speed Mode Transition Band ...................................................................................... 83
Figure 40. Double-Speed Mode Transition Band (Detail) ......................................................................... 84
Figure 41. Double-Speed Mode Passband Ripple .................................................................................... 84
Figure 42. Quad-Speed Mode Stopband Rejection .................................................................................. 84