Cirrus Logic CS42526 - Manual (Page 5)

DS585F2 5
CS42526
Figure 43. Quad-Speed Mode Transition Band ........................................................................................ 84
Figure 44. Quad-Speed Mode Transition Band (Detail) ............................................................................ 84
Figure 45. Quad-Speed Mode Passband Ripple ...................................................................................... 84
Figure 46. Single-Speed (fast) Stopband Rejection .................................................................................. 85
Figure 47. Single-Speed (fast) Transition Band ........................................................................................ 85
Figure 48. Single-Speed (fast) Transition Band (detail) ............................................................................ 85
Figure 49. Single-Speed (fast) Passband Ripple ...................................................................................... 85
Figure 50. Single-Speed (slow) Stopband Rejection ................................................................................ 85
Figure 51. Single-Speed (slow) Transition Band ....................................................................................... 85
Figure 52. Single-Speed (slow) Transition Band (detail) ........................................................................... 86
Figure 53. Single-Speed (slow) Passband Ripple ..................................................................................... 86
Figure 54. Double-Speed (fast) Stopband Rejection ................................................................................ 86
Figure 55. Double-Speed (fast) Transition Band ....................................................................................... 86
Figure 56. Double-Speed (fast) Transition Band (detail) ........................................................................... 86
Figure 57. Double-Speed (fast) Passband Ripple ..................................................................................... 86
Figure 58. Double-Speed (slow) Stopband Rejection ............................................................................... 87
Figure 59. Double-Speed (slow) Transition Band ..................................................................................... 87
Figure 60. Double-Speed (slow) Transition Band (detail) ......................................................................... 87
Figure 61. Double-Speed (slow) Passband Ripple ................................................................................... 87
Figure 62. Quad-Speed (fast) Stopband Rejection ................................................................................... 87
Figure 63. Quad-Speed (fast) Transition Band ......................................................................................... 87
Figure 64. Quad-Speed (fast) Transition Band (detail) ............................................................................. 88
Figure 65. Quad-Speed (fast) Passband Ripple ....................................................................................... 88
Figure 66. Quad-Speed (slow) Stopband Rejection .................................................................................. 88
Figure 67. Quad-Speed (slow) Transition Band ........................................................................................ 88
Figure 68. Quad-Speed (slow) Transition Band (detail) ............................................................................ 88
Figure 69. Quad-Speed (slow) Passband Ripple ...................................................................................... 88
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 25
Table 2. Common PLL Output Clock Frequencies..................................................................................... 25
Table 3. Slave Mode Clock Ratios ............................................................................................................. 26
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 27
Table 5. DAC De-Emphasis ....................................................................................................................... 48
Table 6. Receiver De-Emphasis ................................................................................................................ 48
Table 7. Digital Interface Formats .............................................................................................................. 49
Table 8. ADC One-Line Mode.................................................................................................................... 49
Table 9. DAC One-Line Mode.................................................................................................................... 49
Table 10. RMCK Divider Settings .............................................................................................................. 52
Table 11. OMCK Frequency Settings ........................................................................................................ 52
Table 12. Master Clock Source Select....................................................................................................... 53
Table 13. AES Format Detection ............................................................................................................... 54
Table 14. Receiver Clock Frequency Detection......................................................................................... 55
Table 15. Example Digital Volume Settings ............................................................................................... 58
Table 16. ATAPI Decode ........................................................................................................................... 60
Table 17. Example ADC Input Gain Settings ............................................................................................. 61
Table 18. TXP Output Selection................................................................................................................. 63
Table 19. Receiver Input Selection ............................................................................................................ 63
Table 20. Auxiliary Data Width Selection ................................................................................................... 66
Table 21. External PLL Component Values & Locking Modes .................................................................. 77