Cirrus Logic CS42526 - Manual (Page 46)

46 DS585F2
CS42526
6.3 Power Control (address 02h)
6.3.1 POWER DOWN RECEIVER (PDN_RCVRX)
Default = 10
00 - Receiver and PLL in normal operational mode.
01 - Receiver and PLL held in a reset state. Equivalent to setting 11.
10 - Reserved.
11 - Receiver and PLL held in a reset state. Equivalent to setting 01.
Function:
Places the S/PDIF receiver and PLL in a reset state. It is advised that any change of these bits be
made while the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility
of audible artifacts.
It should be noted that, for Revision C compatibility, PDN_RCVR1 may be set to ‘0’ and receiver op-
eration may be controlled with the PDN_RCVR0 bit.
6.3.2 POWER DOWN ADC (PDN_ADC)
Default = 0
Function:
When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any
change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to elim-
inate the possibility of audible artifacts.
6.3.3 POWER DOWN RESERVE TEST (PDN_RSVD)
Default = 0
Function:
This bit is a reserved power down bit used for test purposes only. For proper operation, this bit must
be set to ‘1’.
6.3.4 POWER DOWN DAC PAIRS (PDN_DACX)
Default = 0
Function:
When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
6.3.5 POWER DOWN (PDN)
Default = 1
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation can occur.
7 6 5 4 3 2 1 0
PDN_RCVR1 PDN_RCVR0 PDN_ADC Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN