Cirrus Logic CS42526 - Manual (Page 70)

70 DS585F2
CS42526
or as a dedicated ADC overflow pin indicating an over-range condition anywhere in the ADC signal
path for either the left or right channel. The Functionx bits determine the operation of the pin. When
configured as a GPO with the output driven low, the driver is a CMOS driver. When configured to iden-
tify an ADC Overflow condition, the driver is an open drain driver requiring a pull-up resistor.
GPO, Drive High Mode - The pin is configured as a general purpose output driven high.
6.28.2 POLARITY SELECT (POLARITY)
Default = 0
Function:
RXP Input - If the pin is configured for an RXP input, the polarity bit is ignored. It is recommended that
in this mode this bit be set to 0.
Mute Mode - If the pin is configured as a dedicated mute output pin, the polarity bit determines the
polarity of the mapped pin according to the following
0 - Active low
1 - Active high
GPO, Drive Low / ADC Overflow Mode - If the pin is configured as a GPO, Drive Low / ADC Overflow
Mode pin, the polarity bit is ignored. It is recommended that in this mode this bit be set to 0.
GPO, Drive High - If the pin is configured as a general-purpose output driven high, the polarity bit is
ignored. It is recommended that in this mode this bit be set to 0.
6.28.3 FUNCTIONAL CONTROL (FUNCTIONX)
Default = 00000
Function:
RXP Input - If the pin is configured for an RXP input, the functional bits are ignored. It is recommended
that in this mode all the functional bits be set to 0.
Mute Mode - If the pin is configured as a dedicated mute pin, the functional bits determine which chan-
nel mutes will be mapped to this pin according to the following table.
0 - Channel mute is not mapped to the RXPx/GPOx pin
1 - Channel mute is mapped to the RXPx/GPOx pin:
GPO, Drive Low / ADC Overflow Mode - If the pin is configured as a GPO, Drive Low / ADC Overflow
Mode pin, the Function1 and Function0 bits determine how the output will behave according to the
RXPx/GPOx Reg Address Function4 Function3 Function2 Function1 Function0
RXP7/GPO7
pin 42
29h M_AOUTA1 M_AOUTB1
M_AOUTA2
M_AOUTB2
M_AOUTA3
M_AOUTB3
Reserved
RXP6/GPO6
pin 43
2Ah
M_AOUTA1
M_AOUTB1
M_AOUTA2 M_AOUTB2
M_AOUTA3
M_AOUTB3
Reserved
RXP5/GPO5
pin 44
2Bh
M_AOUTA1
M_AOUTB1
M_AOUTA2 M_AOUTB2
M_AOUTA3
M_AOUTB3
Reserved
RXP4/GPO4
pin 45
2Ch
M_AOUTA1
M_AOUTB1
M_AOUTA2
M_AOUTB2
M_AOUTA3 M_AOUTB3 Reserved
RXP3/GPO3
pin 46
2Dh
M_AOUTA1
M_AOUTB1
M_AOUTA2
M_AOUTB2
M_AOUTA3 M_AOUTB3 Reserved
RXP2/GPO2
pin 47
2Eh
M_AOUTA1
M_AOUTB1
M_AOUTA2
M_AOUTB2
M_AOUTA3
M_AOUTB3
Reserved Reserved
RXP1/GPO1
pin 48
2Fh
M_AOUTA1
M_AOUTB1
M_AOUTA2
M_AOUTB2
M_AOUTA3
M_AOUTB3
Reserved Reserved