Cirrus Logic CS42526 - Manual (Page 65)

DS585F2 65
CS42526
6.22 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h)
Default = 00000000
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There
are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge
active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge
active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active
mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active
level (Active High or Low) only depends on the INT[1:0] bits located in the register
“Receiver Mode
Control (address 1Eh)” on page 61 .
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
6.23 Channel Status Data Buffer Control (address 24h)
6.23.1 S/PDIF RECEIVER LOCKING MODE (LOCKMX)
Default = 01
00 - Revision C compatibility mode.
01 - Revision D default mode. Provides improved wideband jitter rejection in Double- and Quad-
Speed modes.
10 - High update rate phase detector mode. Provides improved in-band jitter, but increased wideband
jitter. Use this setting for best ADC and DAC performance with clocked from the PLL recovered
clock.
11 - Reserved.
Function:
Selects the mode used by the S/PDIF receiver to lock to the active RXP[7:0] input. Revision C com-
patibility mode is included for backward compatibility with Revision C.
6.23.2 DATA BUFFER SELECT (BSEL)
Default = 0
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
Function:
Selects the data buffer register addresses to contain either User data or Channel Status data.
7 6 5 4 3 2 1 0
UNLOCK1 Reserved QCH1 DETC1 DETU1 Reserved OF1 RERR1
UNLOCK0 Reserved QCH0 DETC0 DETU0 Reserved OF0 RERR0
7 6 5 4 3 2 1 0
LOCKM1 LOCKM0 Reserved Reserved Reserved BSEL CAM CHS