Document Outline

• 1. Pin Descriptions
• 2. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • DAC Analog Characteristics
  • DAC Combined Interpolation & On-Chip Analog FIlter Response
    • Figure 1. DAC Output Test Load
    • Figure 2. Maximum DAC Loading
  • ADC Analog Characteristics
  • ADC Analog Characteristics
  • ADC Digital Filter Characteristics
  • DC Electrical Characteristics
  • Digital Interface Characteristics
  • Switching Characteristics - Serial Audio Port
    • Figure 3. Master Mode Serial Audio Port Timing
    • Figure 4. Slave Mode Serial Audio Port Timing
    • Figure 5. Format 0, Left-Justified up to 24-Bit Data
    • Figure 6. Format 1, I·S up to 24-Bit Data
    • Figure 7. Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data.
  • Switching Characteristics - I·C Control Port
    • Figure 8. Control Port Timing - I·C Format
• 3. Typical Connection Diagram
  • Figure 9. Typical Connection Diagram
• 4. Applications
  • 4.1 Recommended Power-Up Sequence
  • 4.2 System Clocking
    • Table 1. Speed Modes
    • 4.2.1 Master Clock
      • Table 2. Common Clock Frequencies
      • Table 3. MCLK Dividers
    • 4.2.2 Master Mode
      • Figure 10. Master Mode Clocking
    • 4.2.3 Slave Mode
      • Table 4. Slave Mode Serial Bit Clock Ratios
  • 4.3 High-Pass Filter and DC Offset Calibration
  • 4.4 Analog Input Multiplexer, PGA, and Mic Gain
    • Figure 11. Analog Input Architecture
  • 4.5 Input Connections
    • 4.5.1 Pseudo-Differential Input
      • Figure 12. Pseudo-Differential Input Stage
  • 4.6 Output Connections
  • 4.7 Output Transient Control
    • 4.7.1 Power-Up
    • 4.7.2 Power-Down
    • 4.7.3 Serial Interface Clock Changes
  • 4.8 DAC Serial Data Input Multiplexer
  • 4.9 De-Emphasis Filter
    • Figure 13. De-Emphasis Curve
  • 4.10 Internal Digital Loopback
  • 4.11 Mute Control
    • Figure 14. Suggested Active-Low Mute Circuit
  • 4.12 AES3 Transmitter
    • 4.12.1 TxOut Driver
    • 4.12.2 Mono Mode Operation
  • 4.13 I·C Control Port Description and Timing
    • Figure 15. Control Port Timing, I·C Write
    • Figure 16. Control Port Timing, I·C Read
  • 4.14 Status Reporting
  • 4.15 Reset
  • 4.16 Synchronization of Multiple Devices
  • 4.17 Grounding and Power Supply Decoupling
  • 4.18 Package Considerations
• 5. Register Quick Reference
• 6. Register Description
  • 6.1 Chip ID - Register 01h
    • Table 5. Device Revision
  • 6.2 Power Control - Address 02h
    • 6.2.1 Freeze (Bit 7)
      • Table 6. Freeze-able Bits
    • 6.2.2 Power-Down MIC (Bit 3)
    • 6.2.3 Power-Down ADC (Bit 2)
    • 6.2.4 Power-Down DAC (Bit 1)
    • 6.2.5 Power-Down Device (Bit 0)
  • 6.3 DAC Control - Address 03h
    • 6.3.1 DAC Digital Interface Format (Bits 5:4)
      • Table 7. DAC Digital Interface Formats
    • 6.3.2 Mute DAC (Bit 2)
    • 6.3.3 De-Emphasis Control (Bit 1)
      • Table 8. De-Emphasis Control
      • Figure 17. De-Emphasis Curve
  • 6.4 ADC Control - Address 04h
    • 6.4.1 Functional Mode (Bits 7:6)
      • Table 9. Functional Mode Selection
    • 6.4.2 ADC Digital Interface Format (Bit 4)
      • Table 10. ADC Digital Interface Formats
    • 6.4.3 Mute ADC (Bit 2)
    • 6.4.4 ADC High-Pass Filter Freeze (Bit 1)
    • 6.4.5 Master / Slave Mode (Bit 0)
  • 6.5 MCLK Frequency - Address 05h
    • 6.5.1 Master Clock Dividers (Bits 6:4)
      • Table 11. MCLK Frequency
  • 6.6 Signal Selection - Address 06h
    • 6.6.1 DAC SDIN Source (Bit 7)
      • Table 12. DAC SDIN Source Selection
    • 6.6.2 Digital Loopback (Bit 1)
  • 6.7 Channel B PGA Control - Address 07h
    • 6.7.1 Channel B PGA Gain (Bits 5:0)
  • 6.8 Channel A PGA Control - Address 08h
    • 6.8.1 Channel A PGA Gain (Bits 5:0)
      • Table 13. Example Gain and Attenuation Settings
  • 6.9 ADC Input Control - Address 09h
    • 6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
      • Table 14. PGA Soft Cross or Zero Cross Mode Selection
    • 6.9.2 Analog Input Selection (Bit 0)
      • Table 15. Analog Input Selection
  • 6.10 DAC Channel A Volume Control - Address 0Ah
  • 6.11 DAC Channel B Volume Control - Address 0Bh
    • 6.11.1 Volume Control (Bits 7:0)
      • Table 16. Digital Volume Control Example Settings
  • 6.12 DAC Control 2 - Address 0Ch
    • 6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
      • Table 17. DAC Soft Cross or Zero Cross Mode Selection
    • 6.12.2 Invert DAC Output (Bit 5)
  • 6.13 Status - Address 0Dh
    • 6.13.1 E to F C-Buffer Transfer
    • 6.13.2 Clock Error (Bit 3)
    • 6.13.3 ADC Overflow (Bit 1)
    • 6.13.4 ADC Underflow (Bit 0)
  • 6.14 Status Mask - Address 0Eh
  • 6.15 Status Mode MSB - Address 0Fh
  • 6.16 Status Mode LSB - Address 10h
  • 6.17 Transmitter Control 1 - Address 11h
    • 6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6)
    • 6.17.2 C-Data Access Mode (Bit 5)
  • 6.18 Transmitter Control 2 - Address 12h
    • 6.18.1 Transmitter Digital Interface Format (Bits 7:6)
      • Table 18. Transmitter Digital Interface Formats
    • 6.18.2 Transmitter Output Driver Control (Bit 5)
    • 6.18.3 Transmitter Mute Control (Bit 4)
    • 6.18.4 Transmitted Validity Bit Control (Bit 3)
    • 6.18.5 Transmitter Mono/Stereo Operation Control (Bit 2)
    • 6.18.6 Mono Mode CS Data Source (Bit 1)
    • 6.18.7 Mono Mode Channel Selection (Bit 0)
• 7. Parameter Definitions
• 8. DAC Filter Plots
  • Figure 18. DAC Single-Speed Stopband Rejection
  • Figure 19. DAC Single-Speed Transition Band
  • Figure 20. DAC Single-Speed Transition Band
  • Figure 21. DAC Single-Speed Passband Ripple
  • Figure 22. DAC Double-Speed Stopband Rejection
  • Figure 23. DAC Double-Speed Transition Band
  • Figure 24. DAC Double-Speed Transition Band
  • Figure 25. DAC Double-Speed Passband Ripple
  • Figure 26. DAC Quad-Speed Stopband Rejection
  • Figure 27. DAC Quad-Speed Transition Band
  • Figure 28. DAC Quad-Speed Transition Band
  • Figure 29. DAC Quad-Speed Passband Ripple
• 9. ADC Filter Plots
  • Figure 30. ADC Single-Speed Stopband Rejection
  • Figure 31. ADC Single-Speed Stopband Rejection
  • Figure 32. ADC Single-Speed Transition Band (Detail)
  • Figure 33. ADC Single-Speed Passband Ripple
  • Figure 34. ADC Double-Speed Stopband Rejection
  • Figure 35. ADC Double-Speed Stopband Rejection
  • Figure 36. ADC Double-Speed Transition Band (Detail)
  • Figure 37. ADC Double-Speed Passband Ripple
  • Figure 38. ADC Quad-Speed Stopband Rejection
  • Figure 39. ADC Quad-Speed Stopband Rejection
  • Figure 40. ADC Quad-Speed Transition Band (Detail)
  • Figure 41. ADC Quad-Speed Passband Ripple
• 10. External IEC60958-3 Transmitter Components
  • 10.1 IEC60958-3 Transmitter External Components
    • Figure 42. Consumer Output Circuit (VD = 5 V)
    • Figure 43. TTL/CMOS Output Circuit
  • 10.2 Isolating Transformer Requirements
• 11. Channel Status Buffer Management
  • 11.1 IEC60958-3 Channel Status (C) Bit Management
    • Figure 44. Channel Status Data Buffer Structure
    • 11.1.1 Accessing the E Buffer
      • Figure 45. Flowchart for Writing the E Buffer
  • 11.2 Serial Copy Management System (SCMS)
  • 11.3 Channel Status Data E Buffer Access
    • 11.3.1 One-Byte Mode
    • 11.3.2 Two-Byte Mode
• 12. Package Dimensions
• 13. Thermal Characteristics and Specifications
• 14. Ordering Information
• 15. Revision History