Cirrus Logic CS4265 - Manual (Page 23)

DS657F3 23
CS4265
3. TYPICAL CONNECTION DIAGRAM
VLS
10 µF
+3.3V to +5V
47 µF
VQ
FILT+
0.1 µF
10 µF
0.1 µF 10 µF
0.1 µF
+1.8V
to +5V
DGND
VLC
0.1 µF
+1.8V
to +5V
SCL
SDA
RST
2 k
Note 1
LRCK
SDIN1
AGND
Digital Audio
Processor
Micro-
Controller
MCLK
SCLK
0.1 µF
VA VD
* Capacitors must be C0G or equivalent
Digital Audio
Output
2.2nF
AFILTA
AFILTB
MICIN1
MICIN2
Microphone Input 1
Microphone Input 2
2.2nF
SDIN2
TXOUT
TXSDIN
SDOUT
CS4265
2 k
0.1 µF 10 µF
MICBIAS
* *
+3.3V to +5V
SGND Signal Ground
MUTEC
Mute
Drive
AOUTA
AOUTB
470
470
3.3 µF
C
Optional
Analog
Muting
3.3 µF
10 k
10 k C R
ext
R
ext
See Note 2
*
*
AIN1A Left Analog Input 1
10 µF
10 µF
1800 pF
1800 pF
100 k
100 k
100 
100 
AIN1B Right Analog Input 1
*
*
10 µF
10 µF
10 µF
Note 1: Resistors are required for I²C control
port operation
For best response to Fs/2 :
 
470 4
470



ext
ext
R Fs
R
C

This circuitry is intended for applications where the CS4265
connects directly to an unbalanced output of the design . For internal
routing applications please see the DAC Analog Output
Characteristics section for loading limitations.
Note 2 :
R
L
R
L
Note 3
Note 3: The value of R
L
is dictated by the
microphone carteridge.
VA
0.1 µF
AGND
47 k
Note 4: Sets the LSB of the 7-bit chip address.
See the I²C Control Port Description and
Timing section.
Note 4
Figure 9. Typical Connection Diagram