Document Outline

• Ordering Information
• D/A Features
• A/D Features
• System Features
• Stand-Alone Mode Feature Set
• Software Mode Feature Set
• General Description
• 1. Pin Descriptions - Software Mode
• 2. Pin Descriptions - Stand-Alone Mode
• 3. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • DAC Analog Characteristics - Commercial GRADE
  • DAC Analog Characteristics - Automotive Grade
  • DAC Combined Interpolation & On-Chip Analog Filter Response
  • ADC Analog Characteristics - Commercial Grade
  • ADC Analog Characteristics - Automotive Grade
  • ADC Digital Filter Characteristics
  • DC Electrical Characteristics
  • Digital Characteristics
  • Switching Characteristics - Serial Audio Port
    • Figure 1. Master Mode Serial Audio Port Timing
    • Figure 2. Slave Mode Serial Audio Port Timing
    • Figure 3. Format 0, Left Justified up to 24-Bit Data
    • Figure 4. Format 1, I·S up to 24-Bit Data
    • Figure 5. Format 2, Right Justified 16-Bit Data. (Available in Control Port Mode only) Format 3, ...
  • Switching Characteristics - I2C Mode Control Port
    • Figure 6. I2C Mode Control Port Timing
  • Switching Characteristics - SPI Control Port
    • Figure 7. SPI Control Port Timing
• 4. Typical Connection Diagram
  • Figure 8. CS4272 Typical Connection Diagram
• 5. Applications
  • 5.1 Stand-Alone Mode
    • 5.1.1 Recommended Power-Up Sequence
    • 5.1.2 Master/Slave Mode
    • 5.1.3 System Clocking
      • Table 1. Speed Modes
      • Table 2. Crystal Frequencies
      • Table 3. Clock Ratios - Stand Alone Mode With External Crystal
      • Table 4. Clock Ratios - Stand Alone Mode Without External Crystal
    • 5.1.4 16-Bit Auto-Dither
      • Figure 9. ADC 16-Bit Auto-Dither
    • 5.1.5 Auto-Mute
    • 5.1.6 High Pass Filter
    • 5.1.7 Interpolation Filter
    • 5.1.8 Mode Selection & De-Emphasis
      • Table 5. CS4272 Stand-Alone Mode Control
    • 5.1.9 Serial Audio Interface Format Selection
  • 5.2 Control Port Mode
    • 5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode
    • 5.2.2 Master / Slave Mode Selection
    • 5.2.3 System Clocking
      • Table 6. Speed Modes
      • Table 7. Crystal Frequencies
      • Table 8. Clock Ratios - Control Port Mode With External Crystal
      • Table 9. Clock Ratios - Control Port Mode Without External Crystal
    • 5.2.4 Internal Digital Loopback
    • 5.2.5 Dither for 16-Bit Data
      • Figure 10. Example of Dither for 16-Bit Data with 24-Bit Left Justified Format
    • 5.2.6 Auto-Mute
    • 5.2.7 High Pass Filter and DC Offset Calibration
    • 5.2.8 Interpolation Filter
    • 5.2.9 De-Emphasis
    • 5.2.10 Oversampling Modes
  • 5.3 De-Emphasis Filter
    • Figure 11. De-Emphasis Curve
  • 5.4 Analog Connections
    • 5.4.1 Input Connections
      • Figure 12. CS4272 Recommended Analog Input Buffer
      • Figure 13. Full-Scale Analog Input
    • 5.4.2 Output Connections
      • Figure 14. CS4272 Recommended Analog Output Filter
      • Figure 15. Full-Scale Analog Output
  • 5.5 Mute Control
    • Figure 16. Suggested Active-Low Mute Circuit
  • 5.6 Synchronization of Multiple Devices
  • 5.7 Grounding and Power Supply Decoupling
• 6. Control Port Interface
  • 6.1 SPI Mode
    • Figure 17. Control Port Timing, SPI mode
  • 6.2 I·C Mode
    • Figure 18. Control Port Timing, I·C Mode
    • Table 10. Memory Address Pointer (MAP)
• 7. Register Quick Reference
• 8. Register Description
  • 8.1 Mode Control 1 - Address 01h
    • 8.1.1 Functional Mode (Bits 7:6)
      • Table 11. Functional Mode Selection
    • 8.1.2 Ratio Select (Bits 5:4)
    • 8.1.3 Master / Slave Mode (Bit 3)
    • 8.1.4 DAC Digital Interface Format (Bits 2:0)
      • Table 12. DAC Digital Interface Formats
  • 8.2 DAC Control - Address 02h
    • 8.2.1 Auto-Mute (Bit 7)
    • 8.2.2 Interpolation Filter Select (Bit 6)
    • 8.2.3 De-Emphasis Control (Bits 5:4)
      • Table 13. De-Emphasis Mode Selection
      • Figure 19. De-Emphasis Curve
    • 8.2.4 Soft Volume Ramp-Up After Error (Bit 3)
    • 8.2.5 Soft Ramp-Down Before Filter Mode Change (Bit 2)
    • 8.2.6 Invert Signal Polarity (Bits 1:0)
  • 8.3 DAC Volume & Mixing Control - Address 03h
    • 8.3.1 Channel B Volume = Channel A Volume (Bit 6)
    • 8.3.2 Soft Ramp or Zero Cross Enable (Bits 5:4)
      • Table 14. Soft Cross or Zero Cross Mode Selection
    • 8.3.3 ATAPI Channel Mixing and Muting (Bits 3:0)
      • Figure 20. ATAPI Block Diagram
      • Table 15. ATAPI Decode
  • 8.4 DAC Channel A Volume Control - Address 04h
  • 8.5 DAC Channel B Volume Control - Address 05h
    • 8.5.1 Mute (Bit 7)
    • 8.5.2 Volume Control (Bits 6:0)
      • Table 16. Digital Volume Control Example Settings
  • 8.6 ADC Control - Address 06h
    • 8.6.1 Dither for 16-Bit Data (Bit 5)
    • 8.6.2 ADC Digital Interface Format (Bit 4)
      • Table 17. ADC Digital Interface Formats
    • 8.6.3 ADC Channel A & B Mute (Bits 3:2)
    • 8.6.4 Channel A & B High Pass Filter Disable (Bits 1:0)
  • 8.7 Mode Control 2 - Address 07h
    • 8.7.1 Digital Loopback (Bit 4)
    • 8.7.2 AMUTEC = BMUTEC (Bit 3)
    • 8.7.3 Freeze (Bit 2)
    • 8.7.4 Control Port Enable (Bit 1)
    • 8.7.5 Power Down (Bit 0)
  • 8.8 Chip ID - Register 08h
    • 8.8.1 Chip ID (Bits 7:4)
    • 8.8.2 Chip Revision (Bits 3:0)
• 9. Parameter Definitions
• 10. Package Dimensions
• 11. Appendix
  • Figure 21. DAC Single Speed (fast) Stopband Rejection
  • Figure 22. DAC Single Speed (fast) Transition Band
  • Figure 23. DAC Single Speed (fast) Transition Band (detail)
  • Figure 24. DAC Single Speed (fast) Passband Ripple
  • Figure 25. DAC Single Speed (slow) Stopband Rejection
  • Figure 26. DAC Single Speed (slow) Transition Band
  • Figure 27. DAC Single Speed (slow) Transition Band (detail)
  • Figure 28. DAC Single Speed (slow) Passband Ripple
  • Figure 29. DAC Double Speed (fast) Stopband Rejection
  • Figure 30. DAC Double Speed (fast) Transition Band
  • Figure 31. DAC Double Speed (fast) Transition Band (detail)
  • Figure 32. DAC Double Speed (fast) Passband Ripple
  • Figure 33. DAC Double Speed (slow) Stopband Rejection
  • Figure 34. DAC Double Speed (slow) Transition Band
  • Figure 35. DAC Double Speed (slow) Transition Band (detail)
  • Figure 36. DAC Double Speed (slow) Passband Ripple
  • Figure 37. DAC Quad Speed (fast) Stopband Rejection
  • Figure 38. DAC Quad Speed (fast) Transition Band
  • Figure 39. DAC Quad Speed (fast) Transition Band (detail)
  • Figure 40. DAC Quad Speed (fast) Passband Ripple
  • Figure 41. DAC Quad Speed (slow) Stopband Rejection
  • Figure 42. DAC Quad Speed (slow) Transition Band
  • Figure 43. DAC Quad Speed (slow) Transition Band (detail)
  • Figure 44. DAC Quad Speed (slow) Passband Ripple
  • Figure 45. ADC Single Speed Mode Stopband Rejection
  • Figure 46. ADC Single Speed Mode Transition Band
  • Figure 47. ADC Single Speed Mode Transition Band (Detail)
  • Figure 48. ADC Single Speed Mode Passband Ripple
  • Figure 49. ADC Double Speed Mode Stopband Rejection
  • Figure 50. ADC Double Speed Mode Transition Band
  • Figure 51. ADC Double Speed Mode Transition Band (Detail)
  • Figure 52. ADC Double Speed Mode Passband Ripple
  • Figure 53. ADC Quad Speed Mode Stopband Rejection
  • Figure 54. ADC Quad Speed Mode Transition Band
  • Figure 55. ADC Quad Speed Mode Transition Band (Detail)
  • Figure 56. ADC Quad Speed Mode Passband Ripple
  • Table 18. Revision History