Cirrus Logic CS4272 - Manual (Page 44)

CS4272
44 DS593F1
8.7.3 Freeze (Bit 2)
Function:
This function allows modifications to the control port registers without the changes taking effect until
FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneous-
ly, set the FREEZE bit, make all register changes, then clear the FREEZE bit.
8.7.4 Control Port Enable (Bit 1)
Function:
This bit is cleared by default, allowing the device to power-up in Stand-Alone Mode. Control Port
Mode can be accessed by setting this bit. This will allow the operation of the device to be controlled
by the registers and the pin definitions will conform to Control Port Mode. See “Recommended Power-
Up Sequence - Access to Control Port Mode” on page 27.
8.7.5 Power Down (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default
and must be cleared before normal operation in Control Port Mode can occur. The contents of the
control registers are retained when the device is in power-down.
8.8 Chip ID - Register 08h
This is a Read-Only register.
8.8.1 Chip ID (Bits 7:4)
Function:
Chip ID code for the CS4272. Permanently set to 0000b (0h).
8.8.2 Chip Revision (Bits 3:0)
Function:
Chip Revision code for the CS4272.
Revision A is coded as 0000b (0h).
Revision B is coded as 0000b (0h).
B7 B6 B5 B4 B3 B2 B1 B0
PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0