Document Outline

• 1. Pin Descriptions
  • 1.1 I/O Pin Characteristics
• 2. Typical Connection Diagram
  • Figure 1. Typical Connection Diagram
• 3. Characteristic and Specifications
  • Recommended Operating Conditions
  • Absolute Maximum Ratings
  • Analog Input Characteristics
  • ADC Digital Filter Characteristics
  • Analog Output Characteristics
  • Analog Passthrough Characteristics
  • PWM Output Characteristics
  • Headphone Output Power Characteristics
    • Figure 2. Headphone Output Test Load
  • Line Output Voltage Level Characteristics
  • Combined DAC Interpolation and onChip Analog FIlter Response
  • Switching Specifications - Serial Port
    • Figure 3. Serial Audio Interface Timing
  • Switching Specifications - I²C Control Port
    • Figure 4. Control Port Timing - I²C
  • DC Electrical Characteristics
  • Digital Interface Specifications and Characteristics
  • Power Consumption
• 4. Applications
  • 4.1 Overview
    • 4.1.1 Basic Architecture
    • 4.1.2 Line and MIC Inputs
    • 4.1.3 Line and Headphone Outputs
    • 4.1.4 Speaker Driver Outputs
    • 4.1.5 Fixed Function DSP Engine
    • 4.1.6 Beep Generator
    • 4.1.7 Power Management
  • 4.2 Analog Inputs
    • Figure 5. Analog Input Signal Flow
    • 4.2.1 MIC Inputs
      • Figure 6. Single-Ended MIC Configuration
      • Figure 7. Differential MIC Configuration
    • 4.2.2 Automatic Level Control (ALC)
      • Figure 8. ALC
    • 4.2.3 Noise Gate
      • Figure 9. Noise Gate Attenuation
  • 4.3 Analog Outputs
    • Figure 10. DSP Engine Signal Flow
    • Figure 11. PWM Output Stage
    • Figure 12. Analog Output Stage
    • 4.3.1 Beep Generator
      • Figure 13. Beep Configuration Options
    • 4.3.2 Limiter
      • Figure 14. Peak Detect and Limiter
  • 4.4 Analog In to Analog Out Passthrough
    • 4.4.1 Overriding the ADC Power Down
    • 4.4.2 Overriding the PGA Power Down
  • 4.5 PWM Outputs
    • 4.5.1 Mono Speaker Output Configuration
    • 4.5.2 VP Battery Compensation
      • Figure 15. Battery Compensation
  • 4.6 Serial Port Clocking
    • Table 1. MCLK, LRCK Quick Decode
  • 4.7 Digital Interface Formats
    • Figure 16. I²S Format
    • Figure 17. Left-Justified Format
    • Figure 18. Right-Justified Format (DAC only)
    • 4.7.1 DSP Mode
      • Figure 19. DSP Mode Format)
  • 4.8 Initialization
  • 4.9 Recommended Power-up Sequence
  • 4.10 Recommended Power-Down Sequence
  • 4.11 Required Initialization Settings
  • 4.12 Control Port Operation
    • 4.12.1 I²C Control
      • Figure 20. Control Port Timing, I²C Write
      • Figure 21. Control Port Timing, I²C Read
    • 4.12.2 Memory Address Pointer (MAP)
• 5. Register Quick Reference
• 6. Register Description
  • 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
    • 6.1.1 Chip I.D. (Read Only)
    • 6.1.2 Chip Revision (Read Only)
  • 6.2 Power Control 1 (Address 02h)
    • 6.2.1 Power Down ADC Charge Pump
    • 6.2.2 Power Down PGAx
    • 6.2.3 Power Down ADCx
    • 6.2.4 Power Down
  • 6.3 Power Control 2 (Address 03h)
    • 6.3.1 Power Down ADC Override
    • 6.3.2 Power Down MICx
    • 6.3.3 Power Down MIC Bias
  • 6.4 Power Control 3 (Address 04h)
    • 6.4.1 Headphone Power Control
    • 6.4.2 Speaker Power Control
  • 6.5 Clocking Control (Address 05h)
    • 6.5.1 Auto-Detect
    • 6.5.2 Speed Mode
    • 6.5.3 32kHz Sample Rate Group
    • 6.5.4 27 MHz Video Clock
    • 6.5.5 Internal MCLK/LRCK Ratio
    • 6.5.6 MCLK Divide By 2
  • 6.6 Interface Control 1 (Address 06h)
    • 6.6.1 Master/Slave Mode
    • 6.6.2 SCLK Polarity
    • 6.6.3 ADC Interface Format
    • 6.6.4 DSP Mode
    • 6.6.5 DAC Interface Format
    • 6.6.6 Audio Word Length
  • 6.7 Interface Control 2 (Address 07h)
    • 6.7.1 SCLK equals MCLK
    • 6.7.2 SDOUT to SDIN Digital Loopback
    • 6.7.3 Tri-State Serial Port Interface
    • 6.7.4 Speaker/Headphone Switch Invert
    • 6.7.5 MIC Bias Level
  • 6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h)
    • 6.8.1 ADC Input Select
    • 6.8.2 PGA Input Mapping
  • 6.9 Analog and HPF Control (Address 0Ah)
    • 6.9.1 ADCx High-Pass Filter
    • 6.9.2 ADCx High-Pass Filter Freeze
    • 6.9.3 Ch. x Analog Soft Ramp
    • 6.9.4 Ch. x Analog Zero Cross
  • 6.10 ADC HPF Corner Frequency (Address 0Bh)
    • 6.10.1 HPF x Corner Frequency
  • 6.11 Misc. ADC Control (Address 0Ch)
    • 6.11.1 Analog Front-End Volume Setting B=A
    • 6.11.2 Digital MUX
    • 6.11.3 Digital Sum
    • 6.11.4 Invert ADC Signal Polarity
    • 6.11.5 ADC Mute
  • 6.12 Playback Control 1 (Address 0Dh)
    • 6.12.1 Headphone Analog Gain
    • 6.12.2 Playback Volume Setting B=A
    • 6.12.3 Invert PCM Signal Polarity
    • 6.12.4 Master Playback Mute
  • 6.13 Miscellaneous Controls (Address 0Eh)
    • 6.13.1 Passthrough Analog
    • 6.13.2 Passthrough Mute
    • 6.13.3 Freeze Registers
    • 6.13.4 HP/Speaker De-emphasis
    • 6.13.5 Digital Soft Ramp
    • 6.13.6 Digital Zero Cross
  • 6.14 Playback Control 2 (Address 0Fh)
    • 6.14.1 Headphone Mute
    • 6.14.2 Speaker Mute
    • 6.14.3 Speaker Volume Setting B=A
    • 6.14.4 Speaker Channel Swap
    • 6.14.5 Speaker MONO Control
    • 6.14.6 Speaker Mute 50/50 Control
  • 6.15 MICx Amp Control:MIC A (Address 10h) and MIC B (Address 11h)
    • 6.15.1 MIC x Select
    • 6.15.2 MICx Configuration
    • 6.15.3 MICx Gain
  • 6.16 PGAx Vol. and ALCx Transition Ctl.: ALC, PGA A (Address 12h) and ALC, PGA B (Address 13h)
    • 6.16.1 ALCx Soft Ramp Disable
    • 6.16.2 ALCx Zero Cross Disable
    • 6.16.3 PGAx Volume
  • 6.17 Passthrough x Volume: PASSAVOL (Address 14h) and PASSBVOL (Address 15h)
    • 6.17.1 Passthrough x Volume
  • 6.18 ADCx Volume Control: ADCAVOL (Address 16h) and ADCBVOL (Address 17h)
    • 6.18.1 ADCx Volume
  • 6.19 ADCx Mixer Volume: ADCA (Address 18h) and ADCB (Address 19h)
    • 6.19.1 ADC Mixer Channel x Mute
    • 6.19.2 ADC Mixer Channel x Volume
  • 6.20 PCMx Mixer Volume: PCMA (Address 1Ah) and PCMB (Address 1Bh)
    • 6.20.1 PCM Mixer Channel x Mute
    • 6.20.2 PCM Mixer Channel x Volume
  • 6.21 Beep Frequency and On Time (Address 1Ch)
    • 6.21.1 Beep Frequency
    • 6.21.2 Beep On Time
  • 6.22 Beep Volume and Off Time (Address 1Dh)
    • 6.22.1 Beep Off Time
    • 6.22.2 Beep Volume
  • 6.23 Beep and Tone Configuration (Address 1Eh)
    • 6.23.1 Beep Configuration
    • 6.23.2 Beep Mix Disable
    • 6.23.3 Treble Corner Frequency
    • 6.23.4 Bass Corner Frequency
    • 6.23.5 Tone Control Enable
  • 6.24 Tone Control (Address 1Fh)
    • 6.24.1 Treble Gain
    • 6.24.2 Bass Gain
  • 6.25 Master Volume Control: MSTA (Address 20h) and MSTB (Address 21h)
    • 6.25.1 Master Volume Control
  • 6.26 Headphone Volume Control: HPA (Address 22h) and HPB (Address 23h)
    • 6.26.1 Headphone Volume Control
  • 6.27 Speaker Volume Control: SPKA (Address 24h) and SPKB (Address 25h)
    • 6.27.1 Speaker Volume Control
  • 6.28 ADC and PCM Channel Mixer (Address 26h)
    • 6.28.1 PCM Mix Channel Swap
    • 6.28.2 ADC Mix Channel Swap
  • 6.29 Limiter Control 1, Min/Max Thresholds (Address 27h)
    • 6.29.1 Limiter Maximum Threshold
    • 6.29.2 Limiter Cushion Threshold
    • 6.29.3 Limiter Soft Ramp Disable
    • 6.29.4 Limiter Zero Cross Disable
  • 6.30 Limiter Control 2, Release Rate (Address 28h)
    • 6.30.1 Peak Detect and Limiter
    • 6.30.2 Peak Signal Limit All Channels
    • 6.30.3 Limiter Release Rate
  • 6.31 Limiter Attack Rate (Address 29h)
    • 6.31.1 Limiter Attack Rate
  • 6.32 ALC Enable and Attack Rate (Address 2Ah)
    • 6.32.1 ALCx Enable
    • 6.32.2 ALC Attack Rate
  • 6.33 ALC Release Rate (Address 2Bh)
    • 6.33.1 ALC Release Rate
  • 6.34 ALC Threshold (Address 2Ch)
    • 6.34.1 ALC Maximum Threshold
    • 6.34.2 ALC Minimum Threshold
  • 6.35 Noise Gate Control (Address 2Dh)
    • 6.35.1 Noise Gate All Channels
    • 6.35.2 Noise Gate Enable
    • 6.35.3 Noise Gate Threshold and Boost
    • 6.35.4 Noise Gate Delay Timing
  • 6.36 Status (Address 2Eh) (Read Only)
    • 6.36.1 Serial Port Clock Error (Read Only)
    • 6.36.2 DSP Engine Overflow (Read Only)
    • 6.36.3 PCMx Overflow (Read Only)
    • 6.36.4 ADCx Overflow (Read Only)
  • 6.37 Battery Compensation (Address 2Fh)
    • 6.37.1 Battery Compensation
    • 6.37.2 VP Monitor
    • 6.37.3 VP Reference
  • 6.38 VP Battery Level (Address 30h) (Read Only)
    • 6.38.1 VP Voltage Level (Read Only)
  • 6.39 Speaker Status (Address 31h) (Read Only)
    • 6.39.1 Speaker Current Load Status (Read Only)
    • 6.39.2 SPKR/HP Pin Status (Read Only)
  • 6.40 Charge Pump Frequency (Address 34h)
    • 6.40.1 Charge Pump Frequency
• 7. Analog Performance Plots
  • 7.1 Headphone THD+N versus Output Power Plots
    • Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16 W load)
    • Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16 W load)
    • Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32 W load)
    • Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32 W load)
• 8. Example System Clock Frequencies
  • 8.1 Auto Detect Enabled
  • 8.2 Auto Detect Disabled
• 9. PCB Layout Considerations
  • 9.1 Power Supply and Grounding
  • 9.2 QFN Thermal Pad
• 10. ADC and DAC Digital Filters
  • Figure 26. ADC Passband Ripple
  • Figure 27. ADC Stopband Rejection
  • Figure 28. ADC Transition Band
  • Figure 29. ADC Transition Band (Detail)
  • Figure 30. DAC Passband Ripple
  • Figure 31. DAC Stopband
  • Figure 32. DAC Transition Band
  • Figure 33. DAC Transition Band (Detail)
• 11. Parameter Definitions
• 12. Package Dimensions
  • Thermal Characteristics
• 13. Ordering Information
• 14. References
• 15. Revision History