Document Outline

• 1. Characteristics/Specifications
  • Figure 1. Serial Mode Input Timing
  • Figure 2. Direct Stream Digital - Serial Audio Input Timing
  • Figure 3. I2C Control Port Timing
  • Figure 4. SPI Control Port Timing
• 2. Typical Connection DiagramS
  • Figure 5. Typical Connection Diagram - PCM Mode
  • Figure 6. Typical Connection Diagram - DSD Mode
• 3. Register qUICK rEFERENCE
  • 3.1 Mode Control 1 (address 01h)
  • 3.2 Volume and Mixing Control (address 02h)
  • 3.3 Channel A Volume Control (address 03h)
  • 3.4 Channel B Volume Control (address 04h)
  • 3.5 Mode Control 2 (address 05h)
• 4. Register Description
  • 4.1 Mode Control 1 - Address 01h
    • 4.1.1 Auto-Mute (Bit 7)
    • 4.1.2 Digital Interface Formats (Bits 6:4)
    • 4.1.3 De-Emphasis Control (Bits 3:2)
    • 4.1.4 Functional Mode (Bits 1:0)
  • 4.2 Volume and Mixing Control (Address 02h)
    • 4.2.1 Channel A Volume = Channel B Volume (Bit 7)
    • 4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5)
    • 4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0)
  • 4.3 Channel A Volume Control - Address 03h
  • 4.4 Channel B Volume Control - Address 04h
    • 4.4.1 Mute (Bit 7)
    • 4.4.2 Volume Control (Bits 6:0)
  • 4.5 Mode Control 2 - Address 05h
    • 4.5.1 Invert Signal Polarity (Bits 7:6)
    • 4.5.2 Control Port Enable (Bit 5)
    • 4.5.3 Power Down (Bit 4)
    • 4.5.4 AMUTEC = BMUTEC (Bit 3)
    • 4.5.5 Freeze (Bit 2)
    • 4.5.6 Master Clock Divide (Bit 1)
• 5. PIN DESCRIPTION - PCM Data mode
  • Reset - RST
  • Interface Power - VL
  • Serial Audio Data - SDATA
  • Serial Clock - SCLK
  • Left / Right Clock - LRCK
  • Master Clock - MCLK
  • Mode Select - M3, M2, M1 and M0 (Stand-alone Mode)
  • Mode Select - M3 (Control Port Mode)
  • Serial Control Interface Clock - SCL/CCLK (Control Port Mode)
  • Serial Control Data I/O - SDA/CDIN (Control Port Mode)
  • Address Bit / Chip Select - AD0 / CS (Control Port Mode)
  • Positive Voltage Reference - FILT+
  • Common Mode Voltage - CMOUT
  • Channel A and Channel B Mute Control - AMUTEC and BMUTEC
  • Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTA-
  • Analog Ground - AGND
  • Analog Power - VA
• 6. PIN DESCRIPTION - DSD mode
  • DSD Audio Data - DSD_A and DSD_B
  • DSD Mode - DSD_Mode
  • Master Clock - MCLK
  • DSD Serial Clock - DSD_SCLK
    • Table 1. Digital Interface Formats - PCM Modes
    • Table 2. Digital Interface Formats - DSD Mode
    • Table 3. De-Emphasis Mode Selection
    • Table 4. Functional Mode Selection
    • Table 5. Soft Cross or Zero Cross Mode Selection
    • Table 6. ATAPI Decode
    • Table 7. Digital Volume Control
    • Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies
    • Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
    • Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
    • Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options
    • Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options
    • Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options
    • Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options
    • Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options
    • Figure 7. Format 0, Left Justified up to 24-Bit Data
    • Figure 8. Format 1, I2S up to 24-Bit Data
    • Figure 9. Format 2, Right Justified 16-Bit Data
    • Figure 10. Format 3, Right Justified 24-Bit Data
    • Figure 11. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)
    • Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)
    • Figure 13. De-Emphasis Curve
    • Figure 14. ATAPI Block Diagram
• 7. Applications
  • 7.1 Recommended Power-up Sequence for Hardware Mode
  • 7.2 Recommended Power-up Sequence and Access to Control Port Mode
  • 7.3 Analog Output and Filtering
    • Figure 15. CS4391 Output Filter
• 8. Control Port Interface
  • 8.1 SPI Mode
  • 8.2 I2C Mode
    • Table 16. Memory Address Pointer (MAP)
    • Figure 16. Control Port Timing, SPI mode
    • Figure 17. Control Port Timing, I2C Mode
    • Figure 18. Single-Speed Frequency Response
    • Figure 19. Single-Speed Transition Band
    • Figure 20. Single-Speed Transition Band
    • Figure 21. Single-Speed Stopband Rejection
    • Figure 22. Double-Speed Frequency Response
    • Figure 23. Double-Speed Transition Band
    • Figure 24. Double-Speed Transition Band
    • Figure 25. Double-Speed Stopband Rejection
• 9. PARAMETER DEFINITIONS
  • Total Harmonic Distortion + Noise (THD+N)
  • Dynamic Range
  • Interchannel Isolation
  • Interchannel Gain Mismatch
  • Gain Error
  • Gain Drift
• 10. REFERENCES
• 11. PACKAGE DIMENSIONS