Cirrus Logic CS4391 - Manual (Page 22)

CS4391
22 DS335PP4
Serial Clock - SCLK
Pin 4, Input
Function:
Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or
the Mode pins in Hardware Mode. The options are detailed in Figures 7-24.
Left / Right Clock - LRCK
Pin 5, Input
Function:
The Left / Right clock determines which channel is currently being input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or
the Mode pins in Stand-alone Mode. The options are detailed in Figures 7-24
.
Master Clock - MCLK
Pin 6, Input
Function:
The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Sin-
gle Speed Mode; either 128x, 192x 256x, 384x or 512x the input sample rate in Double Speed Mode; or
64x, 96x 128x, 192x or 256 x the input sample rate in Quad Speed Mode. Tables 8-10 illustrate the stan-
dard audio sample rates and the required master clock frequencies.
Note: These clocking ratios are only available in Control Port Mode when the MCLK Divide bit is enabled.
Mode Select - M3, M2, M1 and M0 (Stand-alone Mode)
Pins 7, 8, 9 and 10 Inputs
Function:
The Mode Select Pins, M0-M3, select the operational mode of the device as detailed in Tables 11-15.
Mode Select - M3 (Control Port Mode)
Pin 7, Input
Function:
The Mode Select Pin, M3, is not used in PCM Control Port mode and should be terminated to ground.