Document Outline

• Features & Description
• 1.0 Introduction
  • 1.1 General Description
    • 1.1.1 General Purpose and ISA-Bus Interface
    • 1.1.2 Integrated Memory
    • 1.1.3 802.3 Ethernet MAC Engine
    • 1.1.4 EEPROM Interface
    • 1.1.5 Complete Analog Front End
  • 1.2 System Applications
    • 1.2.1 Motherboard LANs
      • Figure 1. Complete Ethernet Motherboard Solution
    • 1.2.2 Ethernet Adapter Cards
      • Figure 2. Full-Featured ISA Adapter Solution
  • 1.3 Key Features and Benefits
    • 1.3.1 Very Low Cost
    • 1.3.2 High Performance
    • 1.3.3 Low Power and Low Noise
    • 1.3.4 Complete Support
      • Figure 3. Typical ISA Bus Connection Diagram
• 2.0 PIN Description
• 3.0 Functional Description
  • 3.1 Overview
    • 3.1.1 Configuration
    • 3.1.2 Packet Transmission
    • 3.1.3 Packet Reception
  • 3.2 ISA Bus Interface
    • 3.2.1 Memory Mode Operation
    • 3.2.2 I/O Mode Operation
    • 3.2.3 Interrupt Request Signals
      • Table 2. Interrupt Assignments
    • 3.2.4 DMA Signals
      • Table 3. DMA Assignments
  • 3.3 Reset and Initialization
    • 3.3.1 Reset
      • 3.3.1.1 External Reset, or ISA Reset
      • 3.3.1.2 Power-Up Reset
      • 3.3.1.3 Power-Down Reset
      • 3.3.1.4 EEPROM Reset
      • 3.3.1.5 Software Initiated Reset
      • 3.3.1.6 Hardware (HW) Standby or Suspend
      • 3.3.1.7 Software (SW) Suspend
    • 3.3.2 Allowing Time for Reset Operation
    • 3.3.3 Bus Reset Considerations
    • 3.3.4 Initialization
      • Table 4. Default Configuration
      • Table 5. Supported EEPROM Types
  • 3.4 Configurations with EEPROM
    • 3.4.1 EEPROM Interface
      • Table 6. EEPROM Interface
    • 3.4.2 EEPROM Memory Organization
      • Table 7. EEPROM Configuration Block Example
    • 3.4.3 Reset Configuration Block
      • 3.4.3.1 Reset Configuration Block Structure
      • 3.4.3.2 Reset Configuration Block Header
      • 3.4.3.3 Determining the EEPROM Type
      • 3.4.3.4 Checking EEPROM for presence of Reset Configuration Block
      • 3.4.3.5 Determining Number of Bytes in the Reset Configuration Block
    • 3.4.4 Groups of Configuration Data
      • 3.4.4.1 Group Header
      • Figure 4. Group Header
    • 3.4.5 Reset Configuration Block Checksum
    • 3.4.6 EEPROM Example
    • 3.4.7 EEPROM Read-out
      • 3.4.7.1 Determining EEPROM Size
      • 3.4.7.2 Loading Configuration Data
    • 3.4.8 EEPROM Read-out Completion
  • 3.5 Programming the EEPROM
    • Figure 5. EEPROM Command Register Format
    • 3.5.1 EEPROM Commands
      • Table 8. EEPROM Commands
    • 3.5.2 EEPROM Command Execution
    • 3.5.3 Enabling Access to the EEPROM
    • 3.5.4 Writing and Erasing the EEPROM
  • 3.6 Boot PROM Operation
    • 3.6.1 Accessing the Boot PROM
    • 3.6.2 Configuring the CS8900A for Boot PROM Operation
      • Figure 6. Boot PROM Connection Diagram
  • 3.7 Low-Power Modes
    • 3.7.1 Hardware Standby
    • 3.7.2 Hardware Suspend
    • 3.7.3 Software Suspend
      • Table 9. Low-Power Mode Operation
  • 3.8 LED Outputs
    • 3.8.1 LANLED
    • 3.8.2 LINKLED or HC0
      • Table 10. LINKLED/HC0 Pin Operation
    • 3.8.3 BSTATUS or HC1
      • Table 11. BSTATUS/HCI Pin Operation
    • 3.8.4 LED Connection
      • Figure 7. LED Connection Diagram
  • 3.9 Media Access Control
    • 3.9.1 Overview
      • Figure 8. MAC Interface
    • 3.9.2 Frame Encapsulation and Decapsulation
      • 3.9.2.1 Transmission
      • Figure 9. Ethernet Frame Format
      • 3.9.2.2 Reception
      • 3.9.2.3 Enforcing Minimum Frame Size
    • 3.9.3 Transmit Error Detection and Handling
      • 3.9.3.1 Loss of Carrier
      • 3.9.3.2 SQE Error
      • 3.9.3.3 Out-of-Window (Late) Collision
      • 3.9.3.4 Jabber Error
      • 3.9.3.5 Transmit Collision
      • 3.9.3.6 Transmit Underrun
    • 3.9.4 Receive Error Detection and Handling
      • 3.9.4.1 CRC Error
      • 3.9.4.2 Runt Frame
      • 3.9.4.3 Extra Data
      • 3.9.4.4 Dribble Bits and Alignment Error
    • 3.9.5 Media Access Management
      • 3.9.5.1 Collision Avoidance
      • 3.9.5.2 Two-Part Deferral
      • Figure 10. Two-Part Deferral
      • 3.9.5.3 Simple Deferral
      • Figure 11. Simple Deferral
      • 3.9.5.4 Collision Resolution
      • 3.9.5.5 Normal Collisions
      • 3.9.5.6 Late Collisions
      • 3.9.5.7 Backoff
      • 3.9.5.8 Standard Backoff
      • 3.9.5.9 Modified Backoff
      • 3.9.5.10 SQE Test
  • 3.10 Encoder/Decoder (ENDEC)
    • Figure 12. ENDEC
    • 3.10.1 Encoder
    • 3.10.2 Carrier Detection
    • 3.10.3 Clock and Data Recovery
    • 3.10.4 Interface Selection
      • Table 12. Interface Selection
      • 3.10.4.1 10BASE-T Only
      • 3.10.4.2 AUI Only
      • 3.10.4.3 Auto-Select
  • 3.11 10BASE-T Transceiver
    • Figure 13. 10BASE-T Transceiver
    • 3.11.1 10BASE-T Filters
    • 3.11.2 Transmitter
      • Figure 14. Link Pulse Transmission
    • 3.11.3 Receiver
      • 3.11.3.1 Squelch Circuit
      • 3.11.3.2 Extended Range
    • 3.11.4 Link Pulse Detection
    • 3.11.5 Receive Polarity Detection and Correction
    • 3.11.6 Collision Detection
  • 3.12 Attachment Unit Interface (AUI)
    • Figure 15. AUI
    • 3.12.1 AUI Transmitter
    • 3.12.2 AUI Receiver
    • 3.12.3 Collision Detection
  • 3.13 External Clock Oscillator
• 4.0 PACKETPAGE Architecture
  • 4.1 PacketPage Overview
    • 4.1.1 Integrated Memory
    • 4.1.2 Bus Interface Registers
    • 4.1.3 Status and Control Registers
    • 4.1.4 Initiate Transmit Registers
    • 4.1.5 Address Filter Registers
    • 4.1.6 Receive and Transmit Frame Locations
  • 4.2 PacketPage Memory Map
    • Table 13. PacketPage Memory Address Map
  • 4.3 Bus Interface Registers
  • 4.4 Status and Control Registers
    • Figure 16. Status and Control Register Format
    • 4.4.1 Configuration and Control Registers
    • 4.4.2 Status and Event Registers
      • Table 14. PacketPage Register Types
    • 4.4.3 Status and Control Bit Definitions
      • 4.4.3.1 Act-Once Bits
      • 4.4.3.2 Temporal Bits
      • 4.4.3.3 Interrupt Enable Bits and Events
      • Table 15. Interrupt Enable Bits and Events
      • 4.4.3.4 Accept Bits
    • 4.4.4 Status and Control Register Summary
      • Table 16. Status and Control Register Descriptions
  • 4.5 Initiate Transmit Registers
  • 4.6 Address Filter Registers
  • 4.7 Receive and Transmit Frame Locations
    • 4.7.1 Receive PacketPage Locations
    • 4.7.2 Transmit Locations
  • 4.8 Eight and Sixteen Bit Transfers
    • 4.8.1 Transferring Odd-Byte-Aligned Data
      • Figure 17. Odd-Byte Aligned Data
    • 4.8.2 Random Access to CS8900A Memory
  • 4.9 Memory Mode Operation
    • Table 17. Receive/Transmit Memory Locations
    • 4.9.1 Accesses in Memory Mode
    • 4.9.2 Configuring the CS8900A for Memory Mode
    • 4.9.3 Basic Memory Mode Transmit
    • 4.9.4 Basic Memory Mode Receive
    • 4.9.5 Polling the CS8900A in Memory Mode
  • 4.10 I/O Space Operation
    • Table 18. I/O Mode Mapping
    • 4.10.1 Receive/Transmit Data Ports 0 and 1
    • 4.10.2 TxCMD Port
    • 4.10.3 TxLength Port
    • 4.10.4 Interrupt Status Queue Port
    • 4.10.5 PacketPage Pointer Port
      • Figure 18. PacketPage Pointer
    • 4.10.6 PacketPage Data Ports 0 and 1
    • 4.10.7 I/O Mode Operation
    • 4.10.8 Basic I/O Mode Transmit
    • 4.10.9 Basic I/O Mode Receive
    • 4.10.10 Accessing Internal Registers
    • 4.10.11 Polling the CS8900A in I/O Mode
• 5.0 Operation
  • 5.1 Managing Interrupts and Servicing the Interrupt Status Queue
    • Figure 19. Interrupt Status Queue
  • 5.2 Basic Receive Operation
    • 5.2.0.1 Overview
    • Figure 20. Frame Reception
    • 5.2.1 Terminology: Packet, Frame, and Transfer
      • 5.2.1.1 Packet
      • 5.2.1.2 Frame
      • 5.2.1.3 Transfer
    • 5.2.2 Receive Configuration
      • 5.2.2.1 Configuring the Physical Interface
      • Table 19. Physical Interface Configuration
      • 5.2.2.2 Choosing which Frame Types to Accept
      • Table 20. Frame Acceptance Criteria
      • 5.2.2.3 Selecting which Events Cause Interrupts
      • Table 21.
      • Table 22. Registers 3 and B Interrupt Configuration
      • 5.2.2.4 Choosing How to Transfer Frames
      • Table 23. Receive Frame Pre-Processing
    • 5.2.3 Receive Frame Pre-Processing
      • Figure 21. Receive Frame Pre-Processing
      • 5.2.3.1 Destination Address Filtering
      • 5.2.3.2 Early Interrupt Generation
      • Figure 22. Early Interrupt Generation
      • 5.2.3.3 Acceptance Filtering
      • 5.2.3.4 Normal Interrupt Generation
    • 5.2.4 Held vs. DMAed Receive Frames
    • 5.2.5 Buffering Held Receive Frames
    • 5.2.6 Transferring Held Receive Frames
    • 5.2.7 Receive Frame Visibility
    • 5.2.8 Example of Memory Mode Receive Operation
      • Table 24. Example Memory Map
    • 5.2.9 Receive Frame Byte Counter
    • 5.2.10 Receive Frame Address Filtering
      • 5.2.10.1 Individual Address Frames
      • 5.2.10.2 Multicast Frames
      • 5.2.10.3 Broadcast Frames
    • 5.2.11 Configuring the Destination Address Filter
      • Table 25. DA Filtering Options
    • 5.2.12 Hash Filter
      • 5.2.12.1 Hash Filter Operation
      • Figure 23. Hash Filter Operation
    • 5.2.13 Broadcast Frame Hashing Exception
      • Table 26. Contents of RxEvent Upon Various Conditions
  • 5.3 Receive DMA
    • 5.3.1 Overview
    • 5.3.2 Configuring the CS8900A for DMA Operation
      • Table 27. Receive DMA Registers
    • 5.3.3 DMA Receive Buffer Size
    • 5.3.4 Receive-DMA-Only Operation
    • 5.3.5 Committing Buffer Space to a DMAed Frame
    • 5.3.6 DMA Buffer Organization
    • 5.3.7 RxDMAFrame Bit
      • Table 28. RxDMAFrame Bit
    • 5.3.8 Receive DMA Example Without Wrap-Around
      • Figure 24. Example of Frames Stored in DMA Buffer
    • 5.3.9 Receive DMA Operation for RxDMA- Only Mode
      • Figure 25. RxDMA Only Operation
  • 5.4 Auto-Switch DMA
    • 5.4.1 Overview
    • 5.4.2 Configuring the CS8900A for Auto- Switch DMA
    • 5.4.3 Auto-Switch DMA Operation
      • Figure 26. Conditions for Switching to DMA
    • 5.4.4 DMA Channel Speed vs. Missed Frames
    • 5.4.5 Exit From DMA
    • 5.4.6 Auto-Switch DMA Example
      • Figure 27. Example of Auto-Switch DMA
  • 5.5 StreamTransfer
    • 5.5.1 Overview
    • 5.5.2 Configuring the CS8900A for StreamTransfer
      • Table 29. Stream Transfer Configuration
    • 5.5.3 StreamTransfer Operation
    • 5.5.4 Keeping StreamTransfer Mode Active
    • 5.5.5 Example of StreamTransfer
      • Figure 28. Receive Example Without Stream Transfer
      • Figure 29. Receive DMA Configuration Options
    • 5.5.6 Receive DMA Summary
      • Table 30. Receive DMA Configuration Options
  • 5.6 Transmit Operation
    • 5.6.1 Overview
    • 5.6.2 Transmit Configuration
      • 5.6.2.1 Configuring the Physical Interface
      • Table 31. Physical Interface Configuration
      • 5.6.2.2 Selecting which Events Cause Interrupts
      • Table 32. Transmitting Interrupt Configuration
      • Table 33. Transmit Interrupt Configuration
    • 5.6.3 Changing the Configuration
    • 5.6.4 Enabling CRC Generation and Padding
      • Table 34. CRC and Paddling Configuration
    • 5.6.5 Individual Packet Transmission
      • Table 35. Tx Command Configuration
    • 5.6.6 Transmit in Poll Mode
      • Figure 30. Transmit Operation in Polling Mode
    • 5.6.7 Transmit in Interrupt Mode
      • Figure 31. Transmit Operation in Interrupt Mode
    • 5.6.8 Completing Transmission
    • 5.6.9 Rdy4TxNOW vs. Rdy4Tx
    • 5.6.10 Committing Buffer Space to a Transmit Frame
    • 5.6.11 Transmit Frame Length
      • Table 36. Transmit Frame Length
  • 5.7 Full duplex Considerations
  • 5.8 Auto-Negotiation Considerations
• 6.0 Test
  • 6.1 TEST MODES
    • 6.1.1 Loopback & Collision Diagnostic Tests
    • 6.1.2 Internal Tests
    • 6.1.3 External Tests
    • 6.1.4 Loopback Tests
    • 6.1.5 10BASE-T Loopback and Collision Tests
      • Table 37. 10BASE-T Loopback and Collision Tests
    • 6.1.6 AUI Loopback and Collision Tests
      • Table 38. AUI Loopback and Collision Tests
  • 6.2 Boundary Scan
    • 6.2.1 Output Cycle
      • Table 39.
      • Table 40.
    • 6.2.2 Input Cycle
      • Table 41.
      • Table 42.
    • 6.2.3 Continuity Cycle
      • Figure 32. Boundary Scan Continuity Cycle
      • Figure 33. Boundary Scan Timing
• 7.0 Characteristics/Specifications - Commercial
  • 7.1 absolute maximum ratings
  • 7.2 recommended operating conditions
  • 7.3 DC CHARACTERISTICS
  • DC CHARACTERISTICS
  • 7.4 SWITCHING CHARACTERISTICS
  • Figure 34. 16-Bit I/O Read, IOCHRDY not used
  • Figure 35. 16-Bit I/O Read, with IOCHRDY
  • SWITCHING CHARACTERISTICS
  • Figure 36. 16-Bit Memory Read, IOCHRDY not used
  • Figure 37. 16-Bit Memory Read, with IOCHRDY
  • SWITCHING CHARACTERISTICS
  • Figure 38. 16-Bit DMA Read
  • Figure 39. 16-Bit I/O Write
  • SWITCHING CHARACTERISTICS
  • Figure 40. 16-Bit Memory Write
  • Figure 41. 10BASE-T Transmit
  • SWITCHING CHARACTERISTICS
  • Figure 42. 10BASE-T Receive
  • Figure 43. 10BASE-T Link Integrity
  • SWITCHING CHARACTERISTICS
  • Figure 44. AUI Transmit
  • Figure 45. AUI Receive
  • Figure 46. AUI Collision
  • SWITCHING CHARACTERISTICS
  • Figure 47. External Boot PROM Access
  • Figure 48. EEPROM
  • 7.5 10BASE-T Wiring
  • 7.6 AUI Wiring
  • 7.7 QUARTZ CRYSTAL REQUIREMENTS
• 8.0 Characteristics/Specifications - Industrial
  • 8.1 absolute maximum ratings
  • 8.2 recommended operating conditions
  • 8.3 DC CHARACTERISTICS
  • DC CHARACTERISTICS
  • 8.4 SWITCHING CHARACTERISTICS
  • Figure 49. 16-Bit I/O Read, IOCHRDY not used
  • Figure 50. 16-Bit I/O Read, with IOCHRDY
  • SWITCHING CHARACTERISTICS
  • Figure 51. 16-Bit Memory Read, IOCHRDY not used
  • Figure 52. 16-Bit Memory Read, with IOCHRDY
  • SWITCHING CHARACTERISTICS
  • Figure 53. 16-Bit DMA Read
  • Figure 54. 16-Bit I/O Write
  • SWITCHING CHARACTERISTICS
  • Figure 55. 16-Bit Memory Write
  • Figure 56. 10BASE-T Transmit
  • SWITCHING CHARACTERISTICS
  • Figure 57. 10BASE-T Receive
  • Figure 58. 10BASE-T Link Integrity
  • SWITCHING CHARACTERISTICS
  • Figure 59. AUI Transmit
  • Figure 60. AUI Receive
  • Figure 61. AUI Collision
  • SWITCHING CHARACTERISTICS
  • Figure 62. External Boot PROM Access
  • Figure 63. EEPROM
  • 8.5 10BASE-T Wiring
  • 8.6 AUI Wiring
  • 8.7 QUARTZ CRYSTAL REQUIREMENTS
• 9.0 Physical Dimensions
• 10.0 Glossary of Terms
  • 10.1 Acronyms
  • 10.2 Definitions
  • 10.3 Acronyms Specific to the CS8900A
  • 10.4 Definitions Specific to the CS8900A
  • 10.5 Suffixes Specific to the CS8900A.
• Table 1. Revision History