Cirrus Logic CS8900A - Manual (Page 49)

DS271F5 49
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
4.4 Status and Control Registers
The Status and Control registers are the pri-
mary registers used to control and check the
status of the CS8900A. They are organized
into two groups: Configuration/Control Regis-
ters and Status/Event Registers. All Status
and Control Registers are 16-bit words as
shown in Figure 16. Bit 0 indicates whether it
is a Configuration/Control Register (Bit 0 = 1)
or a Status/Event Register (Bit 0 = 0). Bits 0
through 5 provide an internal address code
that describes the exact function of the regis-
ter. Bits 6 through F are the actual Configura-
tion/Control and Status/Event bits.
4.4.1 Configuration and Control Registers
Configuration and Control registers are used
to setup the following:
• how frames will be transmitted and re-
ceived;
• which frames will be transmitted and re-
ceived;
• which events will cause interrupts to the
host processor; and,
• how the Ethernet physical interface will be
configured.
These registers are read/write and are desig-
nated by odd numbers (e.g. Register 1, Regis-
ter 3, etc.).
The Transmit Command Register (TxCMD) is
a special type of register. It appears in two
separate locations in the PacketPage memory
map. The first location, PacketPage base +
0108h, is within the block of Configura-
tion/Control Registers and is read-only. The
second location, PacketPage base + 0144h, is
where the actual transmit commands are is-
sued and is write-only. See Section 4.4.4 on
page 51 (Register 9) and Section 5.6 on
page 99 for a more detailed description of the
TxCMD register.
4.4.2 Status and Event Registers
Status and Event registers report the status of
transmitted and received frames, as well as in-
formation about the configuration of the
CS8900A. They are read-only and are desig-
nated by even numbers (e.g. Register 2, Reg-
ister 4, etc.).
The Interrupt Status Queue (ISQ) is a special
type of Status/Event register. It is located at
PacketPage base + 0120h and is the first reg-
ister the host reads when responding to an In-
terrupt.
A more detailed description of the ISQ can be
found in Section 5.1 on page 78.
Three 10-bit counters are included with the
Status and Event registers. RxMISS counts
missed receive frames, TxCOL counts trans-
mit collisions, and TDR is a time domain reflec-
1 0 3 2 5 4 7 6
10 Register Bits
1 = Control/Configuration
0 = Status/Event
Internal Address
(bits 0 - 5)
16-bit Register Word
Bit Number 9 8 B A D C F E
Figure 16. Status and Control Register Format