Document Outline

• Table of Contents
• List of Figures
• List of Tables
• Chapter 1
  • Introduction
    • Overview
      • Processor
      • Peripherals
      • Memory Map and Register List
        • Global Memory Map
        • Internal Register Map
      • Pin Description
        • External Signal Functions
        • DAI/CODEC/SSI2 Pin Multiplexing
        • Output Bi-Directional Pins
    • Block Diagrams
      • References
• Chapter 2
  • CPU Core
    • Introduction
    • Features
    • Programming Register List
    • Block Diagram
    • Programming Examples
    • Operational Overview
      • MMU
      • TLB
      • Cache
      • Write Buffer
      • Debug Interface
    • CPU Register Definitions
      • ARM720T Core Coprocessor Registers
      • CPU Clocks
        • Real Time Clock (RTC)
        • Real Time Clock Characteristics and Interface Requirements
        • On-Chip PLL
        • PLL Clock Characteristics and Interface Requirements
        • PLL Multiplier for 90MHz Operation
          • Programming Example
    • PLL Multiplier Write Register (PLLW)
    • PLL Multiplier Read Register (PLLR)
      • External 13MHz Clock
      • CPU State Control
        • Standby State
          • Clock Status
    • State Control Register Descriptions
    • Enter the Standby State Register (STDBY)
      • Idle State
    • Enter the Idle State Register (HALT)
      • Power Up Sequence
      • RESET
• Chapter 3
  • Timers
    • Introduction
    • Features
    • Timer Register List
    • Programming Example
    • Operational Overview
      • Free Running Mode
      • Prescale Mode
      • RTC Timer
    • Timer Register Descriptions
    • Timer Counter 1 Data Register (TC1D)
    • Timer Counter 2 Data Register(TC2D)
    • Real Time Clock Data Register (RTCDR)
    • Real Time Clock Match Register (RTCMR)
• Chapter 4
  • Interrupt Controller
    • Introduction
    • Features
    • Interrupt Register List
    • Programming Examples
    • Operational Overview
      • Interrupt Types and Priorities
      • Interrupt Operation
      • Interrupt Listing
      • Interrupt Latencies in Different States
        • Operating State
        • Idle State
        • Standby State
    • Interrupt Register Descriptions
    • Interrupt Status Register 1 (INTSR1)
    • Interrupt Mask Register 1 (INTMR1)
    • Interrupt Mask Register 2 (INTMR2)
    • Interrupt Status Register 3 (INTSR3)
    • Interrupt Mask Register 3 (INTMR3)
    • Battery Low End of Interrupt (BLEOI)
    • Media Change End of Interrupt (MCEOI)
    • Tick End of Interrupt (TEOI)
    • TC1 End of Interrupt (TC1EOI)
    • TC1 End of Interrupt (TC2EOI)
    • RTC Match End of Interrupt (RTCEOI)
    • UART1 Modem Status Changed End of Interrupt (UMSEOI)
    • CODEC End of Interrupt (COEOI)
    • Keyboard End of Interrupt (KBDEOI)
    • SSI2 FIFO Overflow End of Interrupt (SRXEOF)
• Chapter 5
  • System Registers
    • Introduction
    • Features
    • System Register List
    • Programming Example
    • Operational Overview
      • Buzzer
      • Debug Mode
        • MaverickKey™ Unique-ID
    • System Control Register Descriptions
    • System Control Register 1 (SYSCON1)
    • System Control Register 2 (SYSCON2)
    • System Control Register 3 (SYSCON3)
    • System Flag Register 1 (SYSFLG1)
    • System Flag Register 2 (SYSFLG2)
    • Clear all Start-up Reason Flag Register (STFCLR)
    • 32-bit Unique ID Register (UNIQID)
    • Random ID 0 Register, bits 31-0 (RANDID0)
    • Random ID 1 Register, bits 63-32 (RANDID1)
    • Random ID 2 Register, bits 95-64 (RANDID2)
    • Random ID 3 Register, bits 127-96 (RANDID3)
• Chapter 6
  • Processor Support
    • Introduction
    • Features
    • Operational Overview
      • Internal Boot Mode
      • External Boot Mode
      • Endianess
• Chapter 7
  • SDRAM Controller
    • Introduction
    • Features
    • SDRAM Register List
    • Programming Example
    • Operational Overview
      • System Initialization
      • Byte Masks
    • SDRAM Register Descriptions
    • SDRAM Control Register (SDCONF)
    • SDRAM Refresh Period Register (SDRFPR)
• Chapter 8
  • SRAM/Expansion Bus Controller
    • Introduction
    • Features
    • SRAM / Expansion Bus Register List
    • Programming Example
    • Operational Overview
    • SRAM / Expansion Bus Register Descriptions
    • Memory Configuration Register 1 (MEMCFG1)
    • Memory Configuration Register 2 (MEMCFG2)
• Chapter 9
  • LCD Interface
    • Introduction
    • Features
    • LCD Register List
    • Programming Example
    • Operational Overview
      • LCD Controller External Memory
      • LCD DMA Controller
      • Gray Scale
      • Hardware Interface
      • Color LCDs
    • LCD Register Descriptions
    • LCD Control Register (LCDCON)
    • LCD Palette Registers
      • Least Significant Word (PALLSW)
      • Most Significant Word (PALMSW)
    • LCD Frame Buffer Start Address (FBADDR)
• Chapter 10
  • Keyboard Interface
    • Introduction
    • Features
    • Register List
    • Programming Example
    • Operational Overview
      • Keyboard Interrupt Matrix
• Chapter 11
  • General Purpose I/O (GPIO)
    • Introduction
    • Features
    • General Purpose I/O (GPIO) Register List
    • Programming Example
    • Operational Overview
    • Register Descriptions
• Chapter 12
  • PWM Interface
    • Introduction
    • Features
    • Block Diagram
    • PWM (Pulse Width Modulator) Register List
    • Programming Example
    • Operational Overview
    • PWM Register Descriptions
    • Pump Control Register (PMPCON)
• Chapter 13
  • Dedicated LED Flasher
    • Introduction
    • LED Flasher Register List
    • Programming Example
    • Operational Overview
    • Register Definitions
    • LED Flasher Register (LEDFLSH)
• Chapter 14
  • JTAG Interface
    • Introduction
    • Features
    • Operational Overview
      • Boundary Scan
      • Debug Modes
        • Oscillator and PLL Bypass Mode
        • Oscillator and PLL Test Mode
        • Debug/ICE Test Mode
        • Hi-Z (System) Test Mode
      • Software Selectable Test Functionality
• Chapter 15
  • SSI Port
    • Introduction
    • Features
    • SSI Port Register List
    • Programming Example
    • Operational Overview
      • SSI1/ADC Interface
    • SSI Port Register Descriptions
    • Synchronous Serial ADC Interface Data Register (SYNCIO)
      • Register Configuration for Extended Mode
• Chapter 16
  • DAI/CODEC/SSI2
    • Introduction
    • Features
    • Block Diagram
    • DAI/CODEC/SSI2 Register List
    • Programming Example
    • Operational Overview
      • DAI/CODEC/SSI2 MUX
      • DAI Interface
        • DAI Clock Generation
        • Programming the DAI Control and Data Registers
      • Master/Slave SSI2 Interface
        • Read Back of Residual Data
        • Support for Asymmetric Traffic
          • Continuous Data Transfer
          • Discontinuous Clock
          • Error Conditions
          • Clock Polarity
      • CODEC Sound Interface
    • DAI/CODEC/SSI2 Register Descriptions
    • DAI Mode Control Register (DAI64FS)
    • DAI Control Register (DAIR)
      • Full Bit Descriptions
        • DAIEN:
        • LCTM/LRCM/RCTM/RRCM:
        • LCTM:
        • LCRM:
        • RCTM:
        • RCRM:
    • DAI Data Register 0 (DAIDR0)
    • DAI Data Register 1 (DAIDR1)
    • DAI Status Register (DAISR)
      • Full Bit Descriptions
        • RCTS:
        • RCRS:
        • LCTS:
        • LCRS:
        • RCTU:
        • RCRO:
        • LCTU:
        • LCRO:
        • RCNF:
        • LCNF:
        • LCNE:
        • RCNE:
        • FIFO:
    • Synchronous Serial Interface 2 Data Register (SS2DR)
    • Synchronous Serial Interface 2 Pop Residual Byte (SS2POP)
    • CODEC Interface Data Register (CODR)
• Chapter 17
  • UART and SIR Encoder
    • Introduction
    • Features
    • UART and SIR Encoder Register List
    • Programming Example
    • Operational Overview
      • UART1
      • SIR Encoder
      • UART2
    • UART and SIR Encoder Register Descriptions
    • UART Data Registers (UARTDR1 and UARTDR2)
    • Bit Rate and Line Control Registers (UBRLCR1 and UBRLCR2)
• Boot Code
  • Index