Rcne, Fifo, Codec interface data register (codr) – Cirrus Logic EP73xx User Manual

Page 144

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EP7309/11/12 User’s Manual - DS508UM4

Copyright Cirrus Logic, Inc. 2003

DAI/CODEC/SSI2

16

RCNE:

The Right Channel Receive FIFO Not Empty Flag (RCNELCNF) is a read-only bit
which is set when ever the Right Channel Receive FIFO contains one or more entries
of valid data and is cleared when it no longer contains any valid data. This bit can be
polled when using programmed I/O to remove remaining data from the receive
FIFO. This bit does not request an interrupt.

FIFO:

The FIFO Operation Completed (FIFO) Flag is set after the FIFO operation requested
by writing to DAIDR2 as completed. FIFO is automatically cleared when DAIDR2 is
read or written. This bit does not request an interrupt.

SSI2 Registers

Synchronous Serial Interface 2 Data Register (SS2DR)

Address:

0x8000.1500

Definition:

This is the 16-bit-wide data register for the full-duplex master/slave
SSI2 synchronous serial interface. Writing data to this register will
initiate a transfer. Writes need to be word writes and the bottom 16
bits are transferred to the TX FIFO. Reads will be 32 bits as well with
the lower 16 bits containing RX data, and the upper 16-bits should
be ignored. Although the interface is byte-oriented, data is written in
two bytes at a time to allow higher bandwidth transfer. It is up to the
software to assemble the bytes for the data stream in an appropriate
manner.

Note: All reads/writes to this register must be word reads/writes.

Synchronous Serial Interface 2 Pop Residual Byte (SS2POP)

Address:

0x8000.16C0, Read / Write

Definition:

This is a write-only location which will cause the contents of the RX
shift register to be popped into the RX FIFO, thus enabling a residual
byte to be read. The data value written to this register is ignored.
This location should be used in conjunction with the RESVAL and
RESFRM bits in the SYSFLG2 register.

CODEC Register

CODEC Interface Data Register (CODR)

Address:

0x8000.0440, Read / Write

Definition:

The CODR register is an 8-bit read/write register, to be used with
the codec interface. This is selected by the appropriate setting of bit 0
(SERSEL) of the SYSCON2 register. Data written to or read from this
register is pushed or popped onto the appropriate 16-byte FIFO

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