Cirrus Logic EP73xx - Manual (Page 29)

EP7309/11/12 User’s Manual - DS508UM4 2-3
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Copyright Cirrus Logic, Inc. 2003
CPU Core
22
2
;
ldr r0, =0x55555555
mcr p15, 0, r0, c3, c0 ; co-processor register c3
;
;*****************************************************************************
; Tell the MMU where to find the page table.
;*****************************************************************************
;
IMPORT PageTable
ldr r0, =PageTable
mcr p15, 0, r0, c2, c0 ; co-processor register c2
;
;*****************************************************************************
; Enable the MMU.
;*****************************************************************************
;
ldr r0, =0x0000007d ; Cache and Write Buffer enabled in the command
mcr p15, 0, r0, c1, c0 ; co-processor register c1
;
;*****************************************************************************
; There should always be two NOP instructions following the enable or
; disable of the MMU.
;*****************************************************************************
;
mov r0, r0
mov r0, r0
;
;*****************************************************************************
; System state control registers. Standby and Idle states can be entered by
; writes to these register locations.
;*****************************************************************************
;
ldr r0 , =0x80000000 ; base address for Standby and Idle(Halt) registers
mov r1, #0xAA ; value to be written to registers
str r1, [r0,#0x0840] ; write to Standby - system will now enter Standby
state
str r1, [r0,#0x0800] ; write to Idle(Halt) - system, will now enter Idle
state
;