Cirrus Logic EP73xx - Manual (Page 71)

EP7309/11/12 User’s Manual - DS508UM4 5-11
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Copyright Cirrus Logic, Inc. 2003
System Registers
55
5
URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on
the state of the UFIFOEN bit in the UART1 bit rate and line control
register. If the FIFO is disabled, this bit will be set when the RX
holding register is empty. If the FIFO is enabled, the URXFE bit
will be set when the RX FIFO is empty.
UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the
state of the UFIFOEN bit in the UART1 bit rate and line control
register. If the FIFO is disabled, this bit will be set when the TX
holding register is full. If the FIFO is enabled, the UTXFF bit will
be set when the TX FIFO is full.
CRXFE: CODEC RX FIFO empty bit. This will be set if the 16-byte CODEC
RX FIFO is empty.
CTXFF: CODEC TX FIFO full bit. This will be set if the 16-byte CODEC TX
FIFO is full.
SSIBUSY: Synchronous serial interface busy bit. This bit will be set while
data is being shifted in or out of the synchronous serial interface,
when clear data is valid to read.
BOOTBIT[0-1]:These bits indicate the default (power-on reset) bus width of
the ROM interface. See Memory Configuration Registers for more
details on the ROM interface bus width. The state of these bits
reflect the state of
PE[0-1] during power on reset, as shown in the
table below.
ID: Will always read “1” for the EP73xx device
VERID: Version ID bits. These 2 bits determine the version ID for the
EP73xx. Will read “01” for the initial version.
Table 5-5: Default (Power-on Reset) Bus Width Settings
PE[1]
(BOOTBIT1)
PE[0]
(BOOTBIT0)
Boot Option
0 0 32-bit
0 1 8-bit
1 0 16-bit
1 1 Reserved