Cirrus Logic EP73xx User Manual
Page 70
5-10
EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
System Registers
5
Bit Descriptions:
MCDR:
Media changed direct read. This bit reflects the inverted, non-
latched status of the media changed input.
DCDET:
This bit will be set if a non-battery operated power supply is
powering the system (it is the inverted state of the
nEXTPWR
input pin).
WUDR:
Wake up direct read. This bit reflects the non-latched state of the
wakeup signal.
WUON:
This bit will be set if the system has been brought out of the
Standby State by a rising edge on the wakeup signal. It is cleared
by a system reset or by writing to the HALT or STDBY locations.
DID:
Display ID nibble. This 4-bit nibble reflects the latched state of the
four LCD data lines. The state of the four LCD data lines is latched
by the LCDEN bit, and so it will always reflect the last state of
these lines before the LCD controller was enabled.
CTS:
This bit reflects the current status of the clear to send (CTS)
modem control input to UART1.
DSR:
This bit reflects the current status of the data set ready (DSR)
modem control input to UART1.
DCD:
This bit reflects the current status of the data carrier detect (DCD)
modem control input to UART1.
UBUSY1:
UART1 transmitter busy. This bit is set while UART1 is busy
transmitting data, it is guaranteed to remain set until the complete
byte has been sent, including all stop bits.
NBFLG:
New battery flag. This bit will be set if a low to high transition has
occurred on the
nBATCHG
input, it is cleared by writing to the
STFCLR location.
RSTFLG:
Reset flag. This bit will be set if the RESET button has been
pressed, forcing the
nURESET
input low. It is cleared by writing to
the STFCLR location.
PFFLG:
Power Fail Flag. This bit will be set if the system has been reset by
the
nPWRFL
input pin, it is cleared by writing to the STFCLR
location.
CLDFLG: Cold start flag. This bit will be set if the EP73xx has been reset
with a power on reset, it is cleared by writing to the STFCLR
location.
RTCDIV:
This 6-bit field reflects the number of 64 Hz ticks that have passed
since the last increment of the RTC. It is the output of the divide
by 64 chain that divides the 64 Hz tick clock down to 1 Hz for the
RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output.