Interrupt status register 2 (intsr2) – Cirrus Logic EP73xx User Manual
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EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
Interrupt Controller
44
4
Interrupt Status Register 2 (INTSR2)
Address:
0x8000.1240, Read / Write
Definition:
This register is an extension of INTSR1. This interrupt status register
also reflects the current state of the new interrupt sources within the
EP73xx. Each bit is set if the appropriate interrupt is active. The
interrupt assignment is given below.
Bit Descriptions:
RSVD:
Unknown during Read.
KBDINT:
Keyboard interrupt. This interrupt is generated whenever a key is
pressed, from the logical OR of the first 6 or all 8 of the Port A
inputs (depending on the state of the KBD6 bit in the SYSCON2
register. The interrupt request is latched and can be de-asserted by
writing to the KBDEOI location. KBDINT is not deglitched.
SS2RX:
Synchronous serial interface 2 receives FIFO half or greater full
interrupt. This is generated when RX FIFO contains 8 or more
half-words. This interrupt is cleared only when the RX FIFO is
emptied or one SSI2 clock after RX is disabled.
SS2TX:
Synchronous serial interface 2 transmit FIFO less than half empty
interrupt. This is generated when TX FIFO contains fewer than
8 byte pairs. This interrupt gets cleared by loading the FIFO with
more data or disabling the TX. One synchronization clock is
required when disabling the TX side before it takes effect.
UTXINT2: UART2 transmit FIFO half empty interrupt. The function of this
interrupt source depends on whether the UART2 FIFO is enabled.
If the FIFO is disabled (FIFOEN bit is clear in the UART2 bit rate
and line control register), this interrupt will be active when there
is no data in the UART2 TX data holding register and be cleared
by writing to the UART2 data register. If the FIFO is enabled, this
interrupt will be active when the UART2 TX FIFO is half or more
empty and is cleared by filling the FIFO to at least half full. The
FIFO is 16 bytes deep.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
URXINT2
UTXINT2
RSVD
SS2TX
SS2RX
KBDINT