Cirrus Logic EP73xx - Manual (Page 5)

iv EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
Contents
Timer Register Descriptions............................................................................................................................ 3-3
Timer Counter 1 Data Register (TC1D) ..............................................................................................3-3
Timer Counter 2 Data Register(TC2D)...............................................................................................3-3
Real Time Clock Data Register (RTCDR) ..........................................................................................3-3
Real Time Clock Match Register (RTCMR)........................................................................................3-4
Chapter 4. Interrupt Controller
Introduction ....................................................................................................................................................... 4-1
Features .............................................................................................................................................................. 4-1
Interrupt Register List ...................................................................................................................................... 4-1
Programming Examples .................................................................................................................................. 4-2
Operational Overview...................................................................................................................................... 4-3
Interrupt Types and Priorities ................................................................................................................. 4-4
Interrupt Operation................................................................................................................................... 4-4
Interrupt Listing......................................................................................................................................... 4-5
Interrupt Latencies in Different States.................................................................................................... 4-6
Interrupt Register Descriptions ...................................................................................................................... 4-8
Interrupt Status Register 1 (INTSR1) .................................................................................................4-8
Interrupt Mask Register 1 (INTMR1) ................................................................................................4-10
Interrupt Mask Register 2 (INTMR2) ................................................................................................4-12
Interrupt Status Register 3 (INTSR3) ...............................................................................................4-12
Interrupt Mask Register 3 (INTMR3) ................................................................................................4-13
Battery Low End of Interrupt (BLEOI) ...............................................................................................4-13
Media Change End of Interrupt (MCEOI) .........................................................................................4-13
Tick End of Interrupt (TEOI) .............................................................................................................4-13
TC1 End of Interrupt (TC1EOI).........................................................................................................4-13
TC1 End of Interrupt (TC2EOI).........................................................................................................4-14
RTC Match End of Interrupt (RTCEOI).............................................................................................4-14
UART1 Modem Status Changed End of Interrupt (UMSEOI)...........................................................4-14
CODEC End of Interrupt (COEOI) ....................................................................................................4-14
Keyboard End of Interrupt (KBDEOI) ...............................................................................................4-14
SSI2 FIFO Overflow End of Interrupt (SRXEOF) .............................................................................4-14
Chapter 5. System Registers
Introduction ....................................................................................................................................................... 5-1
Features .............................................................................................................................................................. 5-1
System Register List ......................................................................................................................................... 5-2
Programming Example .................................................................................................................................... 5-2
Operational Overview...................................................................................................................................... 5-3
Buzzer.......................................................................................................................................................... 5-3
Debug Mode ............................................................................................................................................... 5-3
System Control Register Descriptions ........................................................................................................... 5-4
System Control Register 1 (SYSCON1) .............................................................................................5-4
System Control Register 2 (SYSCON2) .............................................................................................5-7
System Control Register 3 (SYSCON3) .............................................................................................5-8
System Flag Register 1 (SYSFLG1)...................................................................................................5-9
System Flag Register 2 (SYSFLG2).................................................................................................5-12
Clear all Start-up Reason Flag Register (STFCLR) .........................................................................5-13
32-bit Unique ID Register (UNIQID) .................................................................................................5-13
Random ID 0 Register, bits 31-0 (RANDID0) ...................................................................................5-13
Random ID 1 Register, bits 63-32 (RANDID1) .................................................................................5-13
Random ID 2 Register, bits 95-64 (RANDID2) .................................................................................5-13
Random ID 3 Register, bits 127-96 (RANDID3) ...............................................................................5-13